Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets
oraz
29 sty 2021
O artykule
Data publikacji: 29 sty 2021
Zakres stron: 99 - 110
Otrzymano: 05 maj 2020
Przyjęty: 05 lis 2020
DOI: https://doi.org/10.2478/jaiscr-2021-0007
Słowa kluczowe
© 2021 Maciej Kopczyński et al., published by Sciendo
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
This paper presents FPGA and softcore CPU based solution for large datasets parallel core calculation using rough set methods. Architectures shown in this paper have been tested on two real datasets running presented solutions inside FPGA unit. Tested datasets had 1 000 to 10 000 000 objects. The same operations were performed in software implementation. Obtained results show the big acceleration in computation time using hardware supporting core generation in comparison to pure software implementation.