Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors
, , oraz
01 cze 2011
O artykule
Data publikacji: 01 cze 2011
Zakres stron: 268 - 284
Otrzymano: 09 maj 2011
Przyjęty: 25 maj 2011
DOI: https://doi.org/10.21307/ijssis-2017-439
Słowa kluczowe
© 2011 P. Saha et al., published by Sciendo
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
Saha, P.
Bengal Engineering and Science UniversityShibpur, India
Banerjee, A.
Dept. of ECE, JIS College of EngineeringKalyani, India
Dandapat, A.
Department of ETCE. Jadavpur UniversityIndia
Bhattacharyya, P.
Bengal Engineering and Science UniversityShibpur, India