Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors
, , et
01 juin 2011
À propos de cet article
Publié en ligne: 01 juin 2011
Pages: 268 - 284
Reçu: 09 mai 2011
Accepté: 25 mai 2011
DOI: https://doi.org/10.21307/ijssis-2017-439
Mots clés
© 2011 P. Saha et al., published by Sciendo
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
Saha, P.
Bengal Engineering and Science UniversityShibpur, India
Banerjee, A.
Dept. of ECE, JIS College of EngineeringKalyani, India
Dandapat, A.
Department of ETCE. Jadavpur UniversityIndia
Bhattacharyya, P.
Bengal Engineering and Science UniversityShibpur, India