<abstract xmlns="http://www.w3.org/1999/xhtml"><p>One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.</p></abstract>

One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.

Area–Oriented Technology Mapping for LUT–Based Logic Blocks

International Journal of Applied Mathematics and Computer Science

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

{"article-title":"Area\u2013Oriented Technology Mapping for LUT\u2013Based Logic Blocks"}

One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition...

Area–Oriented Technology Mapping for LUT–Based Logic Blocks

Data publikacji: 04 maj 2017

Zakres stron: 207 - 222

Otrzymano: 06 paź 2015

Przyjęty: 24 paź 2016

DOI: https://doi.org/10.1515/amcs-2017-0015

Słowa kluczowe
SMTBDD, FPGA, synthesis, decomposition

© by Marcin Kubica

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Area–Oriented Technology Mapping for LUT–Based Logic Blocks

Data publikacji: 04 maj 2017

Zakres stron: 207 - 222

Otrzymano: 06 paź 2015

Przyjęty: 24 paź 2016

DOI: https://doi.org/10.1515/amcs-2017-0015

Słowa kluczoweSMTBDD, FPGA, synthesis, decomposition

© by Marcin Kubica

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Słowa kluczowe
SMTBDD, FPGA, synthesis, decomposition