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Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors

P. Saha

P. Saha

Bengal Engineering and Science UniversityShibpur, India
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Saha, P.
, 
A. Banerjee

A. Banerjee

Dept. of ECE, JIS College of EngineeringKalyani, India
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Banerjee, A.
, 
A. Dandapat

A. Dandapat

Department of ETCE. Jadavpur UniversityIndia
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Dandapat, A.
 and 
P. Bhattacharyya

P. Bhattacharyya

Bengal Engineering and Science UniversityShibpur, India
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Bhattacharyya, P.
  
Jun 01, 2011
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Published Online: Jun 01, 2011
Page range: 268 - 284
Received: May 09, 2011
Accepted: May 25, 2011
DOI: https://doi.org/10.21307/ijssis-2017-439
Keywords
© 2011 P. Saha et al., published by Sciendo
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
Language:
English
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1 times per year
Journal Subjects:
Engineering, Introductions and Overviews, Engineering, other
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