Zacytuj

ABC System (2020). https://people.eecs.berkeley.edu/~alanmi/abc/.Search in Google Scholar

Agrawal, R., Borowczak, M. and Vemuri, R. (2019). A state encoding methodology for side-channel security vs. power trade-off exploration, 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID), Delhi, India pp. 70–75.Search in Google Scholar

Altera (2020). Cyclone IV Device Handbook, http://www.altera.com/literature/hb/cyclone-iv/cyclone4-handbook.pdf.Search in Google Scholar

Ardakani, A., Leduc-Primeau, F., Onizawa, N., Hanyu, T. and Gross, W.J. (2017). VLSI implementation of deep neural network using integral stochastic computing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems25(10): 2688–2699.10.1109/TVLSI.2017.2654298Search in Google Scholar

Baranov, S. (1994). Logic Synthesis of Control Automata, Kluwer, Boston, MA.10.1007/978-1-4615-2692-6Search in Google Scholar

Baranov, S. (2008). Logic and System Design of Digital Systems, TUT Press, Tallinn.Search in Google Scholar

Barkalov, A.A. and Barkalov Jr., A.A. (2005). Design of Mealy finite-state machines with the transformation of object codes, International Journal of Applied Mathematics and Computer Science15(1): 151–158.Search in Google Scholar

Barkalov, A. and Titarenko, L. (2009). Logic Synthesis for FSM-based Control Units, Springer, Berlin.10.1007/978-3-642-04309-3Search in Google Scholar

Barkalov, A., Titarenko, L., Kołopieńczyk, M., Mielcarek, K. and Bazydło, G. (2015). Logic Synthesis for FPGA-Based Finite State Machines, Springer, Cham.10.1007/978-3-319-24202-6Search in Google Scholar

Barkalov, A., Titarenko, L., Mazurkiewicz, M. and Krzywicki, K. (2020a). Encoding of terms in EMB-based Mealy FSMs, Applied Sciences10(8): 21.10.3390/app10082762Search in Google Scholar

Barkalov, A., Titarenko, L., Mielcarek, K. and Chmielewski, S. (2020b). Logic Synthesis for FPGA-Based Control Units—Structural Decomposition in Logic Design, Springer, Berlin.10.1007/978-3-030-38295-7Search in Google Scholar

Barkalov, O., Titarenko, L. and Mielcarek, K. (2018). Hardware reduction for LUT-based Mealy FSMs, International Journal of Applied Mathematics and Computer Science28(3): 595–607, DOI: 10.2478/amcs-2018-0046.10.2478/amcs-2018-0046Search in Google Scholar

Benini, L., Bogliolo, A. and Micheli, G. (2000). A survey of design techniques for system-level dynamic power management, IEEE Transactions on Very Large Scale Integration (VLSI) Systems8(3): 299–316.10.1109/92.845896Search in Google Scholar

Benini, L. and De Micheli, G. (1995). State assignment for low power dissipation, IEEE Journal of Solid-State Circuits30(3): 258–268.10.1109/4.364440Search in Google Scholar

Benini, L., De Micheli, G. and Macii, E. (2001). Designing low-power circuits: Practical recipes, IEEE Circuits and Systems Magazine1(1): 6–25.10.1109/7384.928306Search in Google Scholar

Borowik, G. (2018). Optimization on the complementation procedure towards efficient implementation of the index generation function, International Journal of Applied Mathematics and Computer Science28(4): 803–815, DOI: 10.2478/amcs-2018-0061.10.2478/amcs-2018-0061Search in Google Scholar

Brayton, R. and Mishchenko, A. (2010). ABC: An academic industrial-strength verification tool, in T. Touili et al. (Eds), Computer Aided Verification, Springer, Berlin/Heidelberg, pp. 24–40.10.1007/978-3-642-14295-6_5Search in Google Scholar

Brown, B.D. and Card, H.C. (2001). Stochastic neural computation. I: Computational elements, IEEE Transactions on Computers50(9): 891–905.Search in Google Scholar

Choudhury, P. and Pradhan, S. (2012). Power modeling of power gated FSM and its low power realization by simultaneous partitioning and state encoding using genetic algorithm, in H. Rahaman et al. (Eds), Progress in VLSI Design and Test, Springer, Berlin/Heidelberg, pp. 19–29.10.1007/978-3-642-31494-0_3Search in Google Scholar

Chow, S., Ho, Y.-C., Hwang, T. and Liu, C. (1996). Low power realization of finite state machines—A decomposition approach, ACM Transactions on Design Automation of Electronic Systems1(3): 315–340.10.1145/234860.234862Search in Google Scholar

Cong, J. and Yan, K. (2000). Synthesis for FPGAs with embedded memory blocks, Proceedings of the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays, FPGA’00, Monterey, CA, USA, pp. 75–82.Search in Google Scholar

Czerwiński, R. and Kania, D. (2013). Finite State Machine Logic Synthesis for Complex Programmable Logic Devices, Springer, Berlin.10.1007/978-3-642-36166-1Search in Google Scholar

Das, N. and Priya, P.A. (2018). FPGA implementation of reconfigurable finite state machine with input multiplexing architecture using Hungarian method, International Journal of Reconfigurable Computing2018: 1–15.10.1155/2018/6831901Search in Google Scholar

Gajski, D. D., Abdi, S., Gerstlauer, A. and Schirner, G. (2009). Embedded System Design: Modeling, Synthesis and Verification, Springer, Berlin.10.1007/978-1-4419-0504-8Search in Google Scholar

Garcia-Vargas, I. and Senhadji-Navarro, R. (2015). Finite state machines with input multiplexing: A performance study, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems34: 867–871.10.1109/TCAD.2015.2406859Search in Google Scholar

Garcia-Vargas, I., Senhadji-Navarro, R., Jiménez-Moreno, G., Civit-Balcells, A. and Guerra-Gutierrez, P. (2007). ROM-based finite state machine implementation in low cost FPGAs, IEEE International Symposium on Industrial Electronics ISIE 2007, Vigo, Spain, pp. 2342–2347.Search in Google Scholar

Glaser, J., Damm, M., Haase, J. and Grimm, C. (2011). TR-FSM: Transition-based reconfigurable finite state machine, ACM Transactions on Reconfigurable Technology and Systems4(3): 23:1–23:14.10.1145/2000832.2000835Search in Google Scholar

Grout, I. (2008). Digital Systems Design with FPGAs and CPLDs, Elsevier, Oxford.Search in Google Scholar

Kam, T., Villa, T., Brayton, R. and Sangiovanni-Vincentelli, A. (2010). A Synthesis of Finite State Machines: Functional Optimization, Springer, Boston, MA.Search in Google Scholar

Khatri, S. and Gulati, K. (Eds) (2011). Advanced Techniques in Logic Synthesis, Optimizations and Applications, Springer, New York, NY.Search in Google Scholar

Kołopieńczyk, M., Titarenko, L. and Barkalov, A. (2017). Design of EMB-based Moore FSMs, Journal of Circuits, Systems, and Computers26(7): 1–23.10.1142/S0218126617501250Search in Google Scholar

Kubatova, H. and Becvar, M. (2002). FEL-Code: FSM internal state encoding method, Proceedings of the 5th International Workshop on Boolean Problems, Freiberg, Germany, pp. 109–114.Search in Google Scholar

Kubica, M. and Kania, D. (2017). Area-oriented technology mapping for LUT-based logic blocks, International Journal of Applied Mathematics and Computer Science27(1): 207–222, DOI: 10.1515/amcs-2017-0015.10.1515/amcs-2017-0015Search in Google Scholar

Kubica, M., Kania, D. and Kulisz, J. (2019). A technology mapping of FSMs based on a graph of excitations and outputs, IEEE Access7: 16123–16131.10.1109/ACCESS.2019.2895206Search in Google Scholar

LGSynth93 (1993). Benchmark suite, International Workshop on Logic Synthesis, Tahoe City, CA, USA,https://people.engr.ncsu.edu/brglez/CBL/benchmarks/LGSynth93/LGSynth93.tar.Search in Google Scholar

Li, J., Ren, A., Li, Z., Ding, C., Yuan, B., Qiu, Q. and Wang, Y. (2017). Towards acceleration of deep convolutional neural networks using stochastic computing, 22nd Asia and South Pacific Design Automation Conference, ASPDAC, Chiba/Tokyo, Japan, pp. 115–120.Search in Google Scholar

Li, P., Lilja, D.J., Qian, W., Riedel, M.D. and Bazargan, K. (2014). Logical computation on stochastic bit streams with linear finite-state machines, IEEE Transactions on Computers63(6): 1474–1486.10.1109/TC.2012.231Search in Google Scholar

Liu, B., Cai, Y., Zhou, Q., Bian, J. and Hong, X. (2005). FSM decomposition for power gating design automation in sequential circuits, 6th International Conference on ASIC, Shanghai, China, Vol. 2, pp. 944–947.Search in Google Scholar

Machado, L. and Cortadella, J. (2020). Support-reducing decomposition for FPGA mapping, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems39(1): 213–224.10.1109/TCAD.2018.2878187Search in Google Scholar

Maxfield, C. (2004). The Design Warrior’s Guide to FPGAs, Academic Press, Orlando, FL.Search in Google Scholar

Michalski, T. and Kokosiński, Z. (2016). Functional decomposition of combinational logic circuits with PKmin, Technical Transactions: Electrical Engineering113(2-E): 191–202.Search in Google Scholar

Micheli, G.D. (1994). Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York, NY.Search in Google Scholar

Mishchenko, A. and Brayton, R. (2006). Scalable logic synthesis using a simple circuit structure, https://people.eecs.berkeley.edu/~brayton/publications/2006/iwls06_sls.pdf.Search in Google Scholar

Mishchenko, A. and Brayton, R. (2007). SAT-based logic optimization and resynthesis, https://people.eecs.berkeley.edu/~alanmi/publications/2007/tech07_imfs.pdf.Search in Google Scholar

Mishchenko, A., Brayton, R., Jiang, J.-H.R. and Jang, S. (2011). Scalable don’t-care-based logic optimization and resynthesis, ACM Transactions on Reconfigurable Technology and Systems4(4): 23.10.1145/2068716.2068720Search in Google Scholar

Nag, A., Das, S. and Pradhan, S. (2018). Low power FSM synthesis based on automated power and clock gating technique, Journal of Circuits, Systems and Computers28(5), Article ID 1920003.10.1142/S0218126619200032Search in Google Scholar

Nowicka, M., Łuba, T. and Rawski, M. (1999). FPGA-based decomposition of Boolean functions: Algorithms and implementation, 6th International Conference on Advanced Computer Systems, Szczecin, Poland, pp. 502–509.Search in Google Scholar

Opara, A. and Kania, D. (2010). Decomposition-based logic synthesis for PAL-based CPLDs, International Journal of Applied Mathematics and Computer Science20(2): 367–384, DOI: 10.2478/v10006-010-0027-1.10.2478/v10006-010-0027-1Search in Google Scholar

Opara, A., Kubica, M. and Kania, D. (2019). Methods of improving time efficiency of decomposition dedicated at FPGA structures and using BDD in the process of cyber-physical synthesis, IEEE Access7: 20619–20631.10.1109/ACCESS.2019.2898230Search in Google Scholar

PKmin (2020). http://www.pk.edu.pl/~zk/PKmin/PKmin_pomoc-help.zip.Search in Google Scholar

Pradhan, S., Kumar, M. and Chattopadhyay, S. (2011). Low power finite state machine synthesis using power-gating, Integration44(3): 175–184.10.1016/j.vlsi.2011.03.003Search in Google Scholar

Rafla, N.I. and Gauba, I. (2010). A reconfigurable pattern matching hardware implementation using on-chip RAM-based FSM, 53rd IEEE International Midwest Symposium on Circuits and Systems, Boise, ID, USA, pp. 49–52.Search in Google Scholar

Rawski, M., Jozwiak, L., Nowicka M. and Luba T. (1997). Non-disjoint decomposition of Boolean functions and its application in FPGA-oriented technology mapping, Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology, Budapest, Hungary, pp. 24–30.Search in Google Scholar

Rawski, M., Selvaraj, H. and Łuba, T. (2005). An application of functional decomposition in ROM-based FSM implementation in FPGA devices, Journal of System Architecture51(6–7): 423–434.10.1016/j.sysarc.2004.07.004Search in Google Scholar

Rawski, M., Tomaszewicz, P., Borowski, G. and Łuba, T. (2011). Logic synthesis method of digital circuits designed for implementation with embedded memory blocks on FPGAs, in M. Adamski et al. (Eds), Design of Digital Systems and Devices (LNEE 79), Springer, Berlin, pp. 121–144.10.1007/978-3-642-17545-9_5Search in Google Scholar

Scholl, C. (2001). Functional Decomposition with Application to FPGA Synthesis, Kluwer, Boston, MA.10.1007/978-1-4757-3393-8Search in Google Scholar

Sentowich, E., Singh, K., Lavango, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P., Bryton, R. and Sangiovanni-Vincentelli, A. (1992). SIS: A system for sequential circuit synthesis, Technical report, University of California, Berkely, CA.Search in Google Scholar

Sklyarov, V. (2000). Synthesis and implementation of RAM-based finite state machines in FPGAs, Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing, Villach, Austria, pp. 718–728.Search in Google Scholar

Sklyarov, V., Skliarova, I., Barkalov, A. and Titarenko, L. (2014). Synthesis and Optimization of FPGA-Based Systems, Springer, Berlin.10.1007/978-3-319-04708-9Search in Google Scholar

Sutter, G., Todorovich, E., López-Buedo, S. and Boemo, E. (2002). Low-power FSMs in FPGA: Encoding alternatives, Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, Seville, Spain, pp. 363–370.Search in Google Scholar

Testa, E., Amaru, L., Soeken, M., Mishchenko, A., Vuillod, P., Luo, J., Casares, C., Gaillardon, P. and Micheli, G.D. (2019). Scalable Boolean methods in a modern synthesis flow, Design, Automation Test in Europe Conference Exhibition (DATE), Florence, Italy, pp. 1643–1648.Search in Google Scholar

Tiwari, A. and Tomko, K. (2004). Saving power by mapping finite-state machines into embedded memory blocks in FPGAs, Proceedings of the Conference on Design, Automation and Test in Europe, Vol. 2, pp. 916–921.Search in Google Scholar

Vivado (2020). https://www.xilinx.com/products/design-tools/vivado.html.Search in Google Scholar

Wu, X., Pedram, M. and Wang, L. (2000). Multi-code state assignment for low-power design, IEEE Proceedings on Circuits, Devices and Systems147(5): 271–275.10.1049/ip-cds:20000671Search in Google Scholar

Xie, Y., Liao, S., Yuan, B., Wang, Y. and Wang, Z. (2017). Fully-parallel area-efficient deep neural network design using stochastic computing, IEEE Transactions on Circuits and Systems II: Express Briefs64(12): 1382–1386.10.1109/TCSII.2017.2746749Search in Google Scholar

Xilinx (2010). Virtex-4 Family Overview, http://www.xilinx.com/support/documentation/data_sheets/ds112.pdf.Search in Google Scholar

Xilinx (2015). Virtex-5 Family Overview, http://www.xilinx.com/support/documentation/data_sheets/ds100.pdf.Search in Google Scholar

Xilinx (2020a). http://www.xilinx.com.Search in Google Scholar

Xilinx (2020b). ISE Foundation, https://www.xilinx.com/products/design-tools/ise-design-suite.html.Search in Google Scholar

eISSN:
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Język:
Angielski
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Dziedziny czasopisma:
Mathematics, Applied Mathematics