<abstract xmlns="http://www.w3.org/1999/xhtml">

<p>This paper presents an instruction mapping technique for generating a low-level assembly code for digital signal processing algorithms. This technique helps developers to implement retargetable kernel functions with the performance benefits of the low-level assembly languages. The approach is aimed at exceptionally long instruction word (VLIW) architectures, which benefits the most from the proposed method. Mapped algorithms are described by the signal-flow graphs, which are used to find possible parallel operations. The algorithm is converted into low-level code and mapped to the target architecture. This process also introduces the optimization of instruction mapping priority, which leads to the more effective code. The technique was verified on selected kernels, compared to the common programming methods, and proved that it is suitable for VLIW architectures and for portability to other systems.</p>
</abstract>

This paper presents an instruction mapping technique for generating a low-level assembly code for digital signal processing algorithms. This technique helps developers to implement retargetable kernel functions with the performance benefits of the low-level assembly languages. The approach is aimed at exceptionally long instruction word (VLIW) architectures, which benefits the most from the proposed method. Mapped algorithms are described by the signal-flow graphs, which are used to find possible parallel operations. The algorithm is converted into low-level code and mapped to the target architecture. This process also introduces the optimization of instruction mapping priority, which leads to the more effective code. The technique was verified on selected kernels, compared to the common programming methods, and proved that it is suitable for VLIW architectures and for portability to other systems.

Instruction mapping techniques for processors with very long instruction word architectures

Member, IEEE, Department of Radio electronics

Senior Member, IEEE, Department of Radio electronics

Journal of Electrical Engineering

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

This paper presents an instruction mapping technique for generating a low-level assembly code for digital signal processing algorithms. This technique helps...

Instruction mapping techniques for processors with very long instruction word architectures

Data publikacji: 24 gru 2022

Zakres stron: 387 - 395

Otrzymano: 14 wrz 2022

DOI: https://doi.org/10.2478/jee-2022-0053

Słowa kluczowe
digital signal processors, parallel architectures, low-level code, instruction mapping, signal-flow graph

© 2022 Roman Mego et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Instruction mapping techniques for processors with very long instruction word architectures

Data publikacji: 24 gru 2022

Zakres stron: 387 - 395

Otrzymano: 14 wrz 2022

DOI: https://doi.org/10.2478/jee-2022-0053

Słowa kluczowedigital signal processors, parallel architectures, low-level code, instruction mapping, signal-flow graph

© 2022 Roman Mego et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Słowa kluczowe
digital signal processors, parallel architectures, low-level code, instruction mapping, signal-flow graph