A Methodology for the Synthesis and Evaluation of Hardware Accelerators

Data publikacji: 30 sie 2024

Zakres stron: 91 - 100

Otrzymano: 17 cze 2024

Przyjęty: 25 lip 2024

DOI: https://doi.org/10.2478/bipie-2023-0011

Słowa kluczowe

Design Space Exploration (DSE), High-Level Synthesis (HLS), Domain-Specific Accelerator, Power performance area (PPA) analysis, RISC-V

© 2023 Cristian-Tiberius Axinte, published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.