A Methodology for the Synthesis and Evaluation of Hardware Accelerators

Publié en ligne: 30 août 2024

Pages: 91 - 100

Reçu: 17 juin 2024

Accepté: 25 juil. 2024

DOI: https://doi.org/10.2478/bipie-2023-0011

Mots clés

Design Space Exploration (DSE), High-Level Synthesis (HLS), Domain-Specific Accelerator, Power performance area (PPA) analysis, RISC-V

© 2023 Cristian-Tiberius Axinte, published by Sciendo

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