A Methodology for the Synthesis and Evaluation of Hardware Accelerators

Publicado en línea: 30 ago 2024

Páginas: 91 - 100

Recibido: 17 jun 2024

Aceptado: 25 jul 2024

DOI: https://doi.org/10.2478/bipie-2023-0011

Palabras clave

Design Space Exploration (DSE), High-Level Synthesis (HLS), Domain-Specific Accelerator, Power performance area (PPA) analysis, RISC-V

© 2023 Cristian-Tiberius Axinte, published by Sciendo

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