<abstract xmlns="http://www.w3.org/1999/xhtml">

<p>This article presents a synthesis strategy aimed at minimizing the dynamic power consumption of combinational circuits mapped in LUT blocks of FPGAs. The implemented circuits represent the mapping of multi-output functions. Properly selected multi-output functions are described using a new form of the binary decision diagram (BDD), which is an extension of pseudomulti-terminal BDDs (PMTBDDs) in the literature. The essence of limiting power consumption is to include additional parameters during decomposition, such as the switching activity associated with the switching PMTBDD (SWPMTBDD). In addition, we highlight the key importance of circuit optimization methods via non-disjoint decomposition when minimizing power consumption. An algorithm is proposed to assess the effectiveness of decomposition, considering several parameters, such as the number of non-disjoint decompositions as well as that of shared and non-shared bound functions or the switching activity. The results of experiments that demonstrate the effectiveness of the proposed methods are also included.</p>
</abstract>

This article presents a synthesis strategy aimed at minimizing the dynamic power consumption of combinational circuits mapped in LUT blocks of FPGAs. The implemented circuits represent the mapping of multi-output functions. Properly selected multi-output functions are described using a new form of the binary decision diagram (BDD), which is an extension of pseudomulti-terminal BDDs (PMTBDDs) in the literature. The essence of limiting power consumption is to include additional parameters during decomposition, such as the switching activity associated with the switching PMTBDD (SWPMTBDD). In addition, we highlight the key importance of circuit optimization methods via non-disjoint decomposition when minimizing power consumption. An algorithm is proposed to assess the effectiveness of decomposition, considering several parameters, such as the number of non-disjoint decompositions as well as that of shared and non-shared bound functions or the switching activity. The results of experiments that demonstrate the effectiveness of the proposed methods are also included.

Technology Mapping of Multi–Output Functions Leading to the Reduction of Dynamic Power Consumption in FPGAS

Department of Graphics, Computer Vision and Digital Systems

International Journal of Applied Mathematics and Computer Science

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

This article presents a synthesis strategy aimed at minimizing the dynamic power consumption of combinational circuits mapped in LUT blocks of FPGAs. The...

Technology Mapping of Multi–Output Functions Leading to the Reduction of Dynamic Power Consumption in FPGAS

Data publikacji: 23 cze 2023

Zakres stron: 267 - 284

Otrzymano: 27 cze 2022

Przyjęty: 12 sty 2023

DOI: https://doi.org/10.34768/amcs-2023-0020

Słowa kluczowe
low power synthesis, FPGA, switching activity, decomposition, technology mapping

© 2023 Adam Opara et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Technology Mapping of Multi–Output Functions Leading to the Reduction of Dynamic Power Consumption in FPGAS

Data publikacji: 23 cze 2023

Zakres stron: 267 - 284

Otrzymano: 27 cze 2022

Przyjęty: 12 sty 2023

DOI: https://doi.org/10.34768/amcs-2023-0020

Słowa kluczowelow power synthesis, FPGA, switching activity, decomposition, technology mapping

© 2023 Adam Opara et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Słowa kluczowe
low power synthesis, FPGA, switching activity, decomposition, technology mapping