<abstract xmlns="http://www.w3.org/1999/xhtml">

<p>In this paper, different multi-operand adders have been analyzed in terms of propagation delay, power consumption and resource utilization. The functionality of the adders have been verified using Verilog hardware description language and synthesized in Xilinx ISE. The device chosen for implementation is Virtex 6 (XC6VLX240T) with FF1156 package. Simulation results show that Wallace tree adder is the fastest adder and consumes least amount of power. The Wallace tree adder also consumes the least amount of hardware resources as per the synthesis results.</p>
</abstract>

In this paper, different multi-operand adders have been analyzed in terms of propagation delay, power consumption and resource utilization. The functionality of the adders have been verified using Verilog hardware description language and synthesized in Xilinx ISE. The device chosen for implementation is Virtex 6 (XC6VLX240T) with FF1156 package. Simulation results show that Wallace tree adder is the fastest adder and consumes least amount of power. The Wallace tree adder also consumes the least amount of hardware resources as per the synthesis results.

EXPERIMENTAL STUDIES ON MULTI-OPERAND ADDERS

International Journal on Smart Sensing and Intelligent Systems

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

{"article-title":"EXPERIMENTAL STUDIES ON MULTI-OPERAND ADDERS"}

In this paper, different multi-operand adders have been analyzed in terms of propagation delay, power consumption and resource utilization. The functionality...

EXPERIMENTAL STUDIES ON MULTI-OPERAND ADDERS

Data publikacji: 01 cze 2017

Zakres stron: 1 - 14

Otrzymano: 15 lut 2017

Przyjęty: 15 kwi 2017

DOI: https://doi.org/10.21307/ijssis-2017-214

Słowa kluczowe
Multi-operand adders, synthesis results, tree adders, Verilog

© 2017 S. D. Thabah et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

EXPERIMENTAL STUDIES ON MULTI-OPERAND ADDERS

Data publikacji: 01 cze 2017

Zakres stron: 1 - 14

Otrzymano: 15 lut 2017

Przyjęty: 15 kwi 2017

DOI: https://doi.org/10.21307/ijssis-2017-214

Słowa kluczoweMulti-operand adders, synthesis results, tree adders, Verilog

© 2017 S. D. Thabah et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Słowa kluczowe
Multi-operand adders, synthesis results, tree adders, Verilog