<abstract xmlns="http://www.w3.org/1999/xhtml"><p>In this paper, the fully integrated CMOS current mode PLL with current input injects at the place of input or output of the loop filter without summing amplifier circuit. It functions as PPM and PWM circuit is present. In addition, its frequency response is an analysis which electronic tuning BPF and LPF are obtained. The proposed circuit has been designed with 0.18 <italic>μ</italic>m CMOS technology. The simulation results of this circuit can be operated at 2.5 V supply voltage, at center frequency 100 MHz. The linear range of input current can be adjusted from 43 <italic>μ</italic>A to 109 <italic>μ</italic>A, and the corresponding duty cycle of pulse width output is from 93% to 16% and the normalized pulse position is from 0.93 to 0.16. The power dissipation of this circuit is 4.68 mW with the total chip area is 28 <italic>μ</italic>m × 60 <italic>μ</italic>m.</p></abstract>

In this paper, the fully integrated CMOS current mode PLL with current input injects at the place of input or output of the loop filter without summing amplifier circuit. It functions as PPM and PWM circuit is present. In addition, its frequency response is an analysis which electronic tuning BPF and LPF are obtained. The proposed circuit has been designed with 0.18 μm CMOS technology. The simulation results of this circuit can be operated at 2.5 V supply voltage, at center frequency 100 MHz. The linear range of input current can be adjusted from 43 μA to 109 μA, and the corresponding duty cycle of pulse width output is from 93% to 16% and the normalized pulse position is from 0.93 to 0.16. The power dissipation of this circuit is 4.68 mW with the total chip area is 28 μm × 60 μm.

Current mode pulse width modulation/pulse position modulation based on phase lock loop

Faculty of Engineering, Department of Telecommunication

Journal of Electrical Engineering

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

In this paper, the fully integrated CMOS current mode PLL with current input injects at the place of input or output of the loop filter without summing...

Current mode pulse width modulation/pulse position modulation based on phase lock loop

Data publikacji: 06 lip 2017

Zakres stron: 180 - 187

Otrzymano: 18 mar 2017

DOI: https://doi.org/10.1515/jee-2017-0026

Słowa kluczowe
pulse width modulation, pulse position modulation, phase lock loop, current mode

© 2017 Faculty of Electrical Engineering and Information Technology, Slovak University of Technology

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Current mode pulse width modulation/pulse position modulation based on phase lock loop

Data publikacji: 06 lip 2017

Zakres stron: 180 - 187

Otrzymano: 18 mar 2017

DOI: https://doi.org/10.1515/jee-2017-0026

Słowa kluczowepulse width modulation, pulse position modulation, phase lock loop, current mode

© 2017 Faculty of Electrical Engineering and Information Technology, Slovak University of Technology

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Słowa kluczowe
pulse width modulation, pulse position modulation, phase lock loop, current mode