<abstract xmlns="http://www.w3.org/1999/xhtml"><p> The tightened energy requirements when designing state-of-the-art high performance computing systems lead to the increased use of computational accelerators. Intel introduced the Many Integrated Core (MIC) architecture for their line of accelerators and successfully competes with NVIDIA on basis of price/performance and ease of development. Although some codes may be ported successfully to Intel MIC architecture without significant modifications, in order to achieve optimal performance one has to make the best use of the vector processing capabilities of the architecture. In this work we present our implementation of Quasi-Monte Carlo methods for matrix computations specifically optimised for the Intel Xeon Phi accelerators. To achieve optimal parallel efficiency we make use of both MPI and OpenMP.</p></abstract>

The tightened energy requirements when designing state-of-the-art high performance computing systems lead to the increased use of computational accelerators. Intel introduced the Many Integrated Core (MIC) architecture for their line of accelerators and successfully competes with NVIDIA on basis of price/performance and ease of development. Although some codes may be ported successfully to Intel MIC architecture without significant modifications, in order to achieve optimal performance one has to make the best use of the vector processing capabilities of the architecture. In this work we present our implementation of Quasi-Monte Carlo methods for matrix computations specifically optimised for the Intel Xeon Phi accelerators. To achieve optimal parallel efficiency we make use of both MPI and OpenMP.

On the Monte Carlo Matrix Computations on Intel MIC Architecture

, Spain, and ICREA – Catallan Institution for Advanced Research Studies,

Cybernetics and Information Technologies

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

{"article-title":"On the Monte Carlo Matrix Computations on Intel MIC Architecture"}

The tightened energy requirements when designing state-of-the-art high performance computing systems lead to the increased use of computational accelerators....

On the Monte Carlo Matrix Computations on Intel MIC Architecture

Article Category: Special Issue With Selected Papers From The Workshop “Two Years Avitohol: Advanced High Performance Computing Applications 2017

Data publikacji: 16 sty 2018

Zakres stron: 49 - 59

DOI: https://doi.org/10.1515/cait-2017-0054

Słowa kluczowe
Monte Carlo, matrix computations, Intel MIC, High Performance Computing (HPC) scalability

© by Aneta Karaivanova

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

On the Monte Carlo Matrix Computations on Intel MIC Architecture

Article Category: Special Issue With Selected Papers From The Workshop “Two Years Avitohol: Advanced High Performance Computing Applications 2017

Data publikacji: 16 sty 2018

Zakres stron: 49 - 59

DOI: https://doi.org/10.1515/cait-2017-0054

Słowa kluczoweMonte Carlo, matrix computations, Intel MIC, High Performance Computing (HPC) scalability

© by Aneta Karaivanova

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Słowa kluczowe
Monte Carlo, matrix computations, Intel MIC, High Performance Computing (HPC) scalability