This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
M. Han, Ch. Chang, H. Chen, Y. Cheng, and Y. Wu, “Device and Circuit Performance Estimation of Junctionless Bulk FinFETs,” IEEE Transaction on Electron Devices, vol. 60, no. 6, pp.1807-1813, 2013. doi: 10.1109/TED.2013.2256137Search in Google Scholar
A. S. Rawat, and S. K. Gupta, “Potential modeling and performance analysis of junction-less quadruple gate MOSFETs for analog and RF applications,” Microelectronics Journal, vol.66, pp.89-10, 2017. doi:10.1016/j.mejo.2017.06.004Search in Google Scholar
S. Milshtein and C. Liessner, “High speed switch using pairs of pHEMTs with shifted gates,” Microelectronics Journal, vol. 36, pp. 316–318, 2005. doi:10.1016/j.mejo.2005.02.052.Search in Google Scholar
A. Veloso, G. Eneman, A. Keersgieter, D. Jang, H. Mertens, P. Matagne, E. Dentoni, J. Ryckaert, and N. Horiguchi, “Nanosheet FETs and their Potential for Enabling Continued Moore’s Law Scaling,”2021 Electron Devices Technology and Manufacturing Conference (EDTM), 2021. doi: 10.1109/EDTM50988.2021.9420942.Search in Google Scholar
E. Mohapatra, T. P. Dash, J. Jena, S. Das, and C. K. Maiti. “Strain induced Variability Study in Gate All Around Vertically Stacked Horizontal Nanosheet Transistors,”. Physica Scripta, vol.95, no. 6, pp. 065808, 2020. doi: 10.1088/1402-4896/ab89f5Search in Google Scholar
H. Park, W. Choi, M. Pourghaderi, J. Kim, U. Kwon, and D. Kim “NEGF simulations of stacked silicon nanosheet FETs for performance optimization,” 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2019. doi: 10.1109/SISPAD.2019.8870365Search in Google Scholar
S.-T. Chang, “Nanoscale Strained Si/SiGe Hetero-junction Trigate Field Effect Transistors,” Jpn. J. Appl. Phys., vol. 44, no. 7A, pp. 5304-5308, 2005. doi: 10.1143/JJAP.44.5304Search in Google Scholar
S. Reboh, R. Coquand, N. Loubet, N. Bernier, E. Augendre, R. Chao, J. Li, J. Zhang, R. Muthinti, V. Boureau, T. Yamashita, and O. Faynot, “Imaging, Modeling and Engineering of Strain in Gate All Around Nanosheet Transistors,” 2019 IEEE Inter-national Electron Devices Meeting (IEDM), 2019. doi:10.1109/IEDM19573.2019.8993524Search in Google Scholar
K. H. Hong, J. Kim, S. H. Lee, and J. K. Shin, “Strain-Driven Electronic Band Structure Modulation of Si Nanowires,” Nano Letters, vol. 8, no. 5, pp. 1335-1340, 2008. doi:10.1021/nl0734140Search in Google Scholar
N. A. Kumari, and P. Prithvi, “Performance Evaluation of GAA Nanosheet with Varied Geometrical and Process Parameters,” Silicon, vol. 14, pp. 9821-9831, 2022. doi:10.1007/s12633-022-01695-7Search in Google Scholar
C. Usha, and P. Vimala, “Analytical Drain Current Modeling and Simulation of Triple Material Gate All Around Heterojunction TFETs Considering Depletion Regions,” Semiconductors, vol. 54, no. 12, pp. 1634-1640, 2020. doi: 10.1134/S1063782620120398Search in Google Scholar
S. Mukesh, and J. Zhang, “A Review of the Gate All Around Nanosheet FET Process Opportunities,” Electronics, vol. 11, no. 21, pp. 3589 (1-11), 2022. doi: 10.3390/electronics11213589Search in Google Scholar
Q. Zhang and et al., “Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate All Around Si Nanosheets Devices,” Nanomaterials, vol. 11, no. 6, pp. 664, 2021. doi:10.3390/nano11030646Search in Google Scholar
Y. Sun, X. Li, Z. Liu, Y. Liu, X. Li, and Y. Shi, “Vertically stacked nanosheets tree-type reconfigurable transistor with improved ON-current,” IEEE Transactions on Electron Devices, vol. 69, no. 1, pp. 370-374, 2022. doi: 10.1109/TED.2021.3126266Search in Google Scholar
O. Talati, and R. Hosseini, “Device and circuit performance simulation of a new nano scale side contacted field effect diode structure,” Journal of Optoelectronical Nanostructures, vol. 4, no. 3, pp. 17-32, 2019. doi: 20.1001.1.24237361.2019.4.3.2.4Search in Google Scholar
M. Ancona, “Density-gradient theory: a macroscopic approach to quantum confinement and tunneling in semiconductor devices,” Journal of Computational Electronics, vol. 10, no. 1, pp. 65-97, 2011. doi: 10.1007/s10825-011-0356-9Search in Google Scholar
P. Andrei, “Calibration of the Density-Gradient model by using the multidimensional effective-mass Schrödinger equation,” Journal of Computational Electronics, vol. 5, pp. 315-318, 2006. doi: 10.1007/s10825-006-0013-xSearch in Google Scholar
A. Wettstein, Schenk, and W. Fichtner, “Quantum Device Simulation with the Density Gradient Model on Unstructured Grids,” IEEE Transaction on Electron Devices, vol. 48, pp. 279-283, 2001. doi: 10.1109/16.902727Search in Google Scholar
A. Richter, S. Glunz, F. Werner, J. Schmidt, and A. Cuevas, “Improved quantitative description of Auger Recombination in crystalline silicon,” Physical Review B, vol. 86, no. 16, p. 165202, 2012. doi: 10.1103/PhysRevB.86.165202Search in Google Scholar
M. Bavir, A. Abbasi, and A. Orouji, “Dual P+-Wire Double-Gate Junctionless MOSFET with 10‑nm regime for Low Power Applications,” Journal of Electronic Materials, vol.51, pp. 2083-2094, 2022. doi: 10.1007/s11664-022-09462-5Search in Google Scholar