A high electrical performance of DG-MOSFET transistors in 4H-SiC and 6H-SiC 130 nm technology by BSIM3v3 model

[1] J. H. K. Verma, S. Haldar, R.S. Gupta and M. Gupta, “Modeling Simulation of Subthreshold behaviour of Cylindrical Surrounding Double Gate MOSFET for Enhanced Electrostatic Integrity, Superlattices Microstructures 88, 354-364, (2015).10.1016/j.spmi.2015.09.024Search in Google Scholar

[2] A. R. Narang. M. Saxena and M. Gupta, “Modeling of gate underlap junctionless double gate MOSFET as bio-sensor, Materials Science in Semiconductor Processing 71, 240251, (2017).10.1016/j.mssp.2017.08.008Search in Google Scholar

[3] E. N. Cho, Y. H. Shin and I. Yun, “An analytical avalanche breakdown model for double gate MOSFET, Microelectronics Reliability 55(1), 3841, (2015).10.1016/j.microrel.2014.08.019Search in Google Scholar

[4] D. Munteanu, J. L. Autran, and S. Moindjie, “Single event transient effects in Junctionless Double-Gate MOSFETs with Dual-Material Gate investigated by 3D simulation, Microelectronics Reliability 7677, 719-724, (2017).10.1016/j.microrel.2017.07.040Search in Google Scholar

[5] D. Roy and A. Biswas, “Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers, Superlattices Microstructures 110, 114-125, (2017).10.1016/j.spmi.2017.08.055Search in Google Scholar

[6] R. Vaddi, R. P. Agarwal, S. Dasgupta and T. T. Kim, “Design Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device Circuit Co-Design, Journal of Low Power Electronics Applications 1(3), 277-302, (2011).10.3390/jlpea1020277Search in Google Scholar

[7] S. Jilowa, S. S. Gill and G. K. Walia, “Design of 3C-SiC Symmetric Asymmetric Double Gate MOSFET, International Conference on VLSI Systems Architectures, Technology Applications (VLSI-SATA), 1-5, (2016).10.1109/VLSI-SATA.2016.7593052Search in Google Scholar

[8] L. Latu-Romain and O. Maelig, Silicon Carbide One-dimensional Nanostructures Edition 2015- WILEY- ISTE London, United Kingdom, 1-148 (2015).10.1002/9781119081470.ch1Search in Google Scholar

[9] H.-E. Nilsson, K. Bertilsson, E. Dubaric and M. Hjelm, “Numerical Simulation of Field Effect Transistors in 4H 6H-SiC” Proceedings of IEEE, 3rd International Conference on Novel Applications of Wide Bandgap Layers, 199 200, (2001).10.1106/152451102024432Search in Google Scholar

[10] Y. Singh and D. Dwivedi, “A power dual-gate laterally-diffused MOSFET on 4HSiC, International Journal of Electronics Letters 5(4), 385-394, (2016).10.1080/00207217.2016.1242164Search in Google Scholar

[11] D. Tournier, M. Vellvehi, P. Godignon, X. Jorda, and J. Milln, “ Double Gate 180V-128mA/mm SiC-MESFET for Power Switch Applications, Materials Science Forum 527-529, 1243-1246, (2006).10.4028/www.scientific.net/MSF.527-529.1243Search in Google Scholar

[12] R. Mroczynski, N. Kwietniewski and P. Konarski, “Effects of ultra-shallow ion implantation from RF plasma onto electrical properties of 4H-SiC MIS structures with SiOx/HfOx SiOxNy/HfOx double-gate dielectric stacks, Microelectronic Engineering 178, 116121, (2017).10.1016/j.mee.2017.05.017Search in Google Scholar

[13] S. Dash, S. Panda, B. Maji and A. K. Mukhopadhyay “Comparative Thermal Noise Analysis of DG MOSFET Using SiO2, SiC-SiO2, Si3N4-SiO2, 2011 International Conference on Communication Industrial Application, (2011).Search in Google Scholar

[14] M. Hebali, D. Berbara, M. Benzohra, D. Chalabi, A. Saidane and A. B. Bey, “MOSiC (3C, Journal of Engineering Science Technology Review 10(5), 195-198, (2017).10.25103/jestr.105.24Search in Google Scholar

[15] M. Hebali, D. Berbara, M. Benzohra, D. Chalabi and A. Saidane, “A Comparative Study on Electrical Characteristics of MOS (Si0, 5Ge0, 5) MOS (4H-SiC) Transistors in 130 nm Technology with BSIM3v3 Model,” International Journal of Advances in Computer Electronics Engineering, 3(9), 16, (2018).Search in Google Scholar

[16] M. Hebali, D. Berbara, M. A. Abid, M. Benzohra, D. Chalabi, A. Saidane and M. Berka, “ An Ultra Low power High Performance of CMOS (6H-SiC) Current Mirrors in BSIM3v3 130nm Technology, International Journal of Advances in Computer Electronics Engineering 3(11), 18, (2018).Search in Google Scholar

[17] J. Steszewski, A. Jakubowski and M. L. K Pawlowski, “Copmarison of 4H-SiC 6H-SiC MOSFET I-V characteristics simulated with Silvaco Atlas Crosslight Apsys, Journal of Telecommunications & Information Technology 7(3), 93-95, (2007).Search in Google Scholar

[18] C. A. Abdul Nazar and V. Kannan, “Effect of Dual Gate Mosfet on the Decoder Based Demultiplexer, Journal of Theoretical Applied Information Technology 65(2), 589-594, (2014).Search in Google Scholar

[19] Prespice Update – A SPICE Cookbook, Debuts SPICEMOD Helps Model Dual-Gate Mosfets, Undocumented ISSPICE Options (August 1991) http://www.intusoft.com/newsletters.htm.Search in Google Scholar

[20] V. M. Srivastava and G. Singh, “MOSFET Technologies for Double-Pole Four-Throw Radio-Frequency Switch”, Springer Analog Circuits Signal Processing, 1-199, (2014).10.1007/978-3-319-01165-3Search in Google Scholar

[21] R. J. Baker, “CMOS Circuit Design, Layout, EEE Series on Microelectronic Systems, (2000).Search in Google Scholar

[22] Y. Cheng and C. Hu, “MOSFET Modeling & BSIM3 User’s giude, University of California Berkeley, (2002).Search in Google Scholar

[23] W. Liu and X. Jin, “ BSIM3V3. 3 MOSFET User’s Manual, University of California Berkeley, (2005).Search in Google Scholar

[24] S. Bhattacherjee and A. Biswas, “Modeling of threshold voltage subthreshold slope of nanoscale DG MOSFETs”, Semiconductor Science and Technology 23(1), 1-8, (2008).10.1088/0268-1242/23/1/015010Search in Google Scholar

[25] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. ONeill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy and R. Murphy, “Nanowire transistors without junctions, Nature Nanotechnology 5(3), 225-229, (2010).10.1038/nnano.2010.1520173755Search in Google Scholar

[26] W. Meile, J. Xiaoshi, C. Rongyan, L. Xi and J.-H. Lee, “Simulation study on short channel double-gate junctionless field-effect transistors, Journal of Semiconductors 34(3), 034004, 1-8, (2013).10.1088/1674-4926/34/3/034004Search in Google Scholar

[27] R. Hosseini, “Analysis Simulation of a Junctionless Double Gate MOSFET for High-speed Applications, Journal of the Korean Physical Society 67(9), 1615-1618, (2015).10.3938/jkps.67.1615Search in Google Scholar