Impact of lanthanum doped zirconium oxide (LaZrO₂) gate dielectric material on FinFET inverter

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Impacts of gate dielectric SiO2 and LaZrO2 on the performance of n-FinFET device_

	Simulated n-FinFET
Parameters (Vd = 0.75 V, Vg = 0.75 V)	Gate dielectric (LaZrO2) k = 40	Gate dielectric (SiO2) k = 3.9
ION (A)	4.95 × 10−5	1.78 × 10−5
IOFF(A)	3.61 × 10−14	5.02E × 10−13
ION/IOFF	1.37 × 109	3.50 × 107
Vt (V)	0.253	0.207
SS(mV/dec)	60.3	67.02
DIBL(mV/V)	10.1	43
gm (S) (at Vg = 50 mV)	2.42 × 10−4	2.69 × 10−5
VEA (V) (at Vg = 50 mV)	10.7	0.88
TGF (V−1) (at Vg = 50 mV)	24.55	23.2266
gd (S) (at Vg = 50 mV)	1.8 × 10−15	1.95 × 10−12
AV (dB) (at Vg = 50 mV)	183	139.7

Performance analysis of FinFET devices_

	n-FinFET		p-FinFET
Metrics	Lin (Vd = 50 mV)	Sat (Vd = 0.75 V)	Lin (Vd = 50 mV)	Sat (Vd = 0.75 V)
ION (A)	1.37 × 10−5	4.95 × 10−5	1.81 × 10−5	4.54 × 10−5
IOFF(A)	2.64 × 10−14	3.61 × 10−14	2.69 × 10−14	3.98 × 10−14
ION/IOFF	0.51 × 109	1.37 × 109	0.67 × 109	1.14 × 109
SS (mV/dec)	59.9	60.3	59.9	60.9
Vt (V)	0.261	0.253	0.262	0.253
gm (S)	5.88 × 10−5	2.42 × 10−4	4.71 × 10−5	2.33 × 10−4
TGF (V−1)	24.68	24.55	24.65	24.37
DIBL (mV/V)	10.1	12.3

Important TCAD device parameters for an inverter design_

Process parameters	Value
Design rule unit lambda (µm)	0.007
Thickness of substrate region (µm)	0.03
Height of fin (µm)	0.024
Thickness of gate oxide (µm)	0.0011
S/D doping concentration (donor) for nMOS (cm-3)	3E20
S/D doping concentration (acceptor) for pMOS (cm−3)	3E20
Supply voltage, Vd (V)	0.8 V
Thickness of buried oxide (µm)	0.02
Thickness of poly-silicon gate (µm)	0.002
Thickness of ILD dielectric (µm)	0.008
Thickness of ILD Metal 1(µm)	0.008
Lateral characteristic length of S/D doping of nMOS (µm)	0.004
Vertical characteristic length of S/D doping of nMOS (µm)	0.003
Doping concentration in p-type substrate (cm−3)	1E16
Doping concentration in body (cm−3)	1E17

Impact on noise margin due to temperature and voltage variation for simulated inverter circuit

	Temperature (kelvin)						Voltage (volts)
Gate dielectric permittivity value(k)	273 K		300 K		398 K		0.4 V		0.8 V		1.2 V
	NMH (V)	NML (V)	NMH (V)	NML (V)	NMH (V)	NML (V)	NMH (V)	NML (V)	NMH (V)	NML (V)	NMH (V)	NML (V)
40(LaZrO2)	0.4	0.377	0.375	0.375	0.35	0.35	0.195	0.12	0.375	0.375	0.55	0.55

Structural parameters used in simulation *As per ITRS dimensions (Wikipedia 14nm process, 2020)_

	Simulation work
Device’s performance parameters	(n-FinFET)	(p-FinFET)
Gate length, Lg (nm)	14	14
Transistor fin pitch (nm)	42	42
Transistor fin width, WFin (nm)	8	8
Transistor fin height, HFin (nm)	24	24
Workfunction, WF (eV)	4.6	4.6
Gate dielectric permittivity, k	40	40
Physical oxide thickness (nm)	1.1	1.1
Supply voltage, Vd (volts)	0.75	0.75