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Pt/Al2O3/HfO2/Ti/TiN bi-layer RRAM device for imply–inhibit logic applications: Unveiling the resistive potential by experiment and simulation

Nithya Natarajan

Nithya Natarajan

Department of Electrical and Electronics Engineering, Kumaraguru College of TechnologyCoimbatore-641049, India
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Natarajan, Nithya
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Paramasivam Kuppusamy

Paramasivam Kuppusamy

Department of Electrical and Electronics Engineering, Kumaraguru College of TechnologyCoimbatore-641049, India
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Kuppusamy, Paramasivam
  
Mar 31, 2025
Pt/Al2O3/HfO2/Ti/TiN bi-layer RRAM device for imply–inhibit logic applications: Unveiling the resistive potential by experiment and simulation's Cover Image
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Article Category: Research Article
Published Online: Mar 31, 2025
Page range: 196 - 209
Received: Feb 05, 2025
Accepted: May 25, 2025
DOI: https://doi.org/10.2478/msp-2025-0016
Keywords
© 2025 Nithya Natarajan and Paramasivam Kuppusamy, published by Sciendo
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Figure 1

Step-by-step process of fabricating the proposed RRAM device.
Step-by-step process of fabricating the proposed RRAM device.

Figure 2

Proposed 1T-1R structure for imply–inhibit logic gates.
Proposed 1T-1R structure for imply–inhibit logic gates.

Figure 3

(a) Cross-sectional HRTEM image of the Pt/Al2O3/HfO2/Ti/TiNbi-layer RRAM structure. (b) The closer view of layer deposition and its interface.
(a) Cross-sectional HRTEM image of the Pt/Al2O3/HfO2/Ti/TiNbi-layer RRAM structure. (b) The closer view of layer deposition and its interface.

Figure 4

XRD pattern of Al2O3 and HfO2 nanoparticles.
XRD pattern of Al2O3 and HfO2 nanoparticles.

Figure 5

XPS spectra of the Al2O3/HfO2 bi-layer structure. (a) Al2p, (b) Hf4f peaks, (c) O 1-s peak of the Al2O3 layer, and (d) O 1-s peak of the HfO2 layer.
XPS spectra of the Al2O3/HfO2 bi-layer structure. (a) Al2p, (b) Hf4f peaks, (c) O 1-s peak of the Al2O3 layer, and (d) O 1-s peak of the HfO2 layer.

Figure 6

Resistive switching characteristics of the device unit and distribution of the SET and RESET voltages. (a) Typical resistive switching characteristics of the device, (b) durability of the device unit, (c) memory retention of HRS and LRS for 103 s with a read voltage of 0.2 V, and (d) resistive switching mechanism of the Pt/Al2O3/HfO2/Ti/TiN RRAM during the SET and RESET process.
Resistive switching characteristics of the device unit and distribution of the SET and RESET voltages. (a) Typical resistive switching characteristics of the device, (b) durability of the device unit, (c) memory retention of HRS and LRS for 103 s with a read voltage of 0.2 V, and (d) resistive switching mechanism of the Pt/Al2O3/HfO2/Ti/TiN RRAM during the SET and RESET process.

Figure 7

Resistive switching characteristics of the Pt/Al2O3/HfO2/TiN device. (a) Typical I–V characteristics of the device, (b) forming behavior, (c) durability of the device, and (d) memory retention of HRS and LRS for 103 s with a read voltage of 0.2 V.
Resistive switching characteristics of the Pt/Al2O3/HfO2/TiN device. (a) Typical I–V characteristics of the device, (b) forming behavior, (c) durability of the device, and (d) memory retention of HRS and LRS for 103 s with a read voltage of 0.2 V.

Figure 8

(a) Cycle-to-cycle variation in I–V characteristics of Pt/Al2O3/HfO2/TiN device, (b) cycle-to-cycle variation in I–V characteristics of the Pt/Al2O3/HfO2/Ti/TiN device, (c) and (d) SET and RESET voltage distribution of the Pt/Al2O3/HfO2/TiN device, and (e) and (f) SET and RESET voltage distribution of the Pt/Al2O3/HfO2/Ti/TiN device.
(a) Cycle-to-cycle variation in I–V characteristics of Pt/Al2O3/HfO2/TiN device, (b) cycle-to-cycle variation in I–V characteristics of the Pt/Al2O3/HfO2/Ti/TiN device, (c) and (d) SET and RESET voltage distribution of the Pt/Al2O3/HfO2/TiN device, and (e) and (f) SET and RESET voltage distribution of the Pt/Al2O3/HfO2/Ti/TiN device.

Figure 9

The circuit diagram for a 1-bit adder with a combination of inhibit, imply, and XNOR logic gates.
The circuit diagram for a 1-bit adder with a combination of inhibit, imply, and XNOR logic gates.

Figure 10

(a) Hysteresis curve of the simulation results superimposed on the experimental results, (b) simulated waveform of imply logic, (c) simulated waveform of inhibit logic, (d) simulated waveform of XNOR logic, (e) simulated waveform of half-adder, and (f) simulated waveform of full-adder.
(a) Hysteresis curve of the simulation results superimposed on the experimental results, (b) simulated waveform of imply logic, (c) simulated waveform of inhibit logic, (d) simulated waveform of XNOR logic, (e) simulated waveform of half-adder, and (f) simulated waveform of full-adder.

Figure 11

PDP and transistor count comparison between proposed logic style and CMOS logic style.
PDP and transistor count comparison between proposed logic style and CMOS logic style.

Truth table for simulated logic gates_

Inputs Logic gates
A B NOT AND OR IMPLY INHIBIT NAND NOR XOR XNOR
0 0 1 0 0 0 1 1 1 0 1
0 1 1 0 1 1 1 1 0 1 0
1 0 0 0 1 0 0 1 0 1 0
1 1 0 1 1 0 1 0 0 0 1

Comparison between proposed memristor-based logic circuits and other logic circuits_

Function Logic circuits Component Power (µW) Delay (ps)
XOR 1T2M-based logic [19] 1T + 6R 156 48.7
Universal logic [20] 2T + 2R + 1 resistor 25.77 16.74
MeMOS logic [21] 4T + 6R 2.08 30.6
CMOS logic [22] 8T + 2 inverter 28.42 87.5 × 103
Proposed logic 4T + 4R 1.955 25.6
XNOR 1T2M-based logic 1T + 6R 168 51.7
Universal logic 2T + 2R + 1 resistor 36.28 —
MeMOS logic 4T + 6R 2.41 31.11
Proposed logic 3T + 3R 1.182 23.68
NOT 1T2M-based logic 1T + 2R 142 45.03
MeMOS logic 2T 0.5 18.7
CMOS logic 2T 0.086 13.04
Proposed logic 1T + 1R 0.916 7.262
Half-adder MeMOS logic 8T + 8R 8.07 98.05
Proposed logic 6T + 6R 1.996 42.5
1-bit Adder 1T2M-based logic 3T + 16R 307 57.93
Universal logic 16T + 10R + 2 resistor 134 69.3
MeMOS logic 16T + 18R 17.87 212.3
Proposed logic 7T + 7R 2.775 74.2
IMPLY CMOS logic 6T 0.218 38.91
Proposed logic 1T + 1R 0.463 7.221
INHIBIT CMOS logic 6T 0.228 42.38
Proposed logic 1T + 1R 0.45 13.49
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Materials Sciences, Materials Sciences, other, Nanomaterials, Functional and Smart Materials, Materials Characterization and Properties
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