<abstract xmlns="http://www.w3.org/1999/xhtml">

<p>The needs of the chip are growing on a daily basis as extremely large size integrated circuits evolve fast. As a result, the network-on-chip (NoC) was suggested and successfully developed to address the issue of communication on-chip. Current research focuses on NoC topology and routing algorithms that have a substantial influence on network performance. Because low power is a priority, the Mesh-of-Tree (MoT) architecture is preferable. However, certain MoT routers may perform extensive communication activities, which means they consume more power and are more likely to become hotspots. To improve power consumption, we presented a Simpler Mesh-of-Tree (SMoT) architecture based on MoT in this study. We also suggested a path-wise routing scheme for the Internet of Things, which takes into account both network traffic and the shortest path between two points. By altering the direction of data forwarding to reduce network latency, our methodology spreads communication over the whole network. When compared to MoT, our suggested strategy can lower network power consumption by 5.39%–23.3% while also reducing network latency by 4.23%–27.28%.</p>
</abstract>

The needs of the chip are growing on a daily basis as extremely large size integrated circuits evolve fast. As a result, the network-on-chip (NoC) was suggested and successfully developed to address the issue of communication on-chip. Current research focuses on NoC topology and routing algorithms that have a substantial influence on network performance. Because low power is a priority, the Mesh-of-Tree (MoT) architecture is preferable. However, certain MoT routers may perform extensive communication activities, which means they consume more power and are more likely to become hotspots. To improve power consumption, we presented a Simpler Mesh-of-Tree (SMoT) architecture based on MoT in this study. We also suggested a path-wise routing scheme for the Internet of Things, which takes into account both network traffic and the shortest path between two points. By altering the direction of data forwarding to reduce network latency, our methodology spreads communication over the whole network. When compared to MoT, our suggested strategy can lower network power consumption by 5.39%–23.3% while also reducing network latency by 4.23%–27.28%.

A Path-Wise Scheme for Simpler Mesh-of-Tree Model in Network-on-Chip Designs

International Journal of Advanced Network, Monitoring and Controls

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

{"article-title":"A Path-Wise Scheme for Simpler Mesh-of-Tree Model in Network-on-Chip Designs"}

The needs of the chip are growing on a daily basis as extremely large size integrated circuits evolve fast. As a result, the network-on-chip (NoC) was...

Processor configuration
CPU_TYPE	Timing		Timing
CPU_NUMS	16		64
NoC configuration
TOPOLOGY	Mesh	MoT	SMoT
SCHEDULING_POLICY	xy routing scheme	deterministic routing scheme	path-wise routing scheme
BENCHMARK	PARSEC	PARSEC	PARSEC

A Path-Wise Scheme for Simpler Mesh-of-Tree Model in Network-on-Chip Designs

Published Online: May 24, 2023

Page range: 10 - 15

DOI: https://doi.org/10.2478/ijanmc-2022-0022

Keywords
Noc, Low Power, Routing Scheme

© 2022 Yu Lu, published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Environmental setup

A Path-Wise Scheme for Simpler Mesh-of-Tree Model in Network-on-Chip Designs

Published Online: May 24, 2023

Page range: 10 - 15

DOI: https://doi.org/10.2478/ijanmc-2022-0022

KeywordsNoc, Low Power, Routing Scheme

© 2022 Yu Lu, published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Environmental setup

Keywords
Noc, Low Power, Routing Scheme