A Path-Wise Scheme for Simpler Mesh-of-Tree Model in Network-on-Chip Designs

The needs of the chip are growing on a daily basis as extremely large size integrated circuits evolve fast. As a result, the network-on-chip (NoC) was suggested and successfully developed to address the issue of communication on-chip. Current research focuses on NoC topology and routing algorithms that have a substantial influence on network performance. Because low power is a priority, the Mesh-of-Tree (MoT) architecture is preferable. However, certain MoT routers may perform extensive communication activities, which means they consume more power and are more likely to become hotspots. To improve power consumption, we presented a Simpler Mesh-of-Tree (SMoT) architecture based on MoT in this study. We also suggested a path-wise routing scheme for the Internet of Things, which takes into account both network traffic and the shortest path between two points. By altering the direction of data forwarding to reduce network latency, our methodology spreads communication over the whole network. When compared to MoT, our suggested strategy can lower network power consumption by 5.39%–23.3% while also reducing network latency by 4.23%–27.28%.