Otwarty dostęp

Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider


Zacytuj

R. Parameshwaran, G. Lakshminarayanan, M. Shakunthala, and M. Vimal Kumar, “A Novel Design of Ultra-Low-power 32/33 Pre-scaler based on modified 2/3 TSPC Pre-scaler for PLL Applications”, Journal of Critical Reviews, vol. 7(2), pp. 820-823, 2020.Search in Google Scholar

P. Anirvinnan, Vaishnavi S. Parashar, D. Aneesh Bharadwaj, and B.S. Premananda, “Low-power AVLS-TSPC based 2/3 Pre-Scaler”, International Journal of Engineering and Advanced Technology, vol. 9(1), pp. 6687-6693, 2019.Search in Google Scholar

K. Deepthi and P. Srikanth, “Design of 18-Transistor TSPC Flip-Flop based on Logic Structure Reduction Schemes”, International Journal of Research, vol. 8(5), pp. 1049-1055, 2019.Search in Google Scholar

Y. Kishore Kumar, G. Leenendra Chowdary, and C.R.S. Hanuman, “Low Power Single Phase Clock Multiband Flexible Divider using Low Power Techniques”, International Journal of Electronics Communication & Instrumentation Engineering Research and Development, vol. 4(1), pp. 27-36, 2014.Search in Google Scholar

S. Surya, “Novel Design of wideband TSPC divide-by-32/33 Dual Modulus Pre-scaler”, International Journal for Technological Research in Engineering, vol. 3(10), pp. 2846-2849, 2016.Search in Google Scholar

B.S. Premananda, T.N. Dhanush, Vaishnavi S. Parashar, and D. Aneesh Bharadwaj, “Design and Implementation of High Frequency and Low-Power Phase-locked Loop”, U.Porto Journal of Engineering, vol. 7(4), pp. 70-86, 2021.Search in Google Scholar

M.G. Anish, and C. Riboy, “Design and Analysis of Power and Area Efficient 2/3 Prescaler Using ETSPC Logic”, International Journal of Scientific & Engineering Research, vol. 4(8), pp. 1-6, 2013.Search in Google Scholar

B.S. Premananda, Shaswat Valivati, and Abdur Rehman, “TSPC-AVLS Based Low-Power 16/17 Dual Modulus Prescaler Design”, IETE Journal of Research, 2023.Search in Google Scholar

M. Mounika, B.V. Krishnaveni, and P. Raveen, “Design of PLL Using Multi Modulus divide by 32/33 Prescaler in CMOS 45-nm Technology”, International Journal & Magazine of Engineering, Technology, Management, and Research, vol. 2(10), pp. 360-365, 2015.Search in Google Scholar

Agrakshi and Suman Rani, “Low Power Design Techniques in CMOS Circuits: A Review”, International Journal for Research in Applied Science & Engineering Technology, vol. 3(2), pp. 330-335, 2015. Search in Google Scholar

B.S. Premananda, and M.G. Ganavi, “Performance Analysis of Low-power 8-Tap FIR Filter using PFAL”, International Journal of Innovative Technology and Exploring Engineering, vol. 8(8), pp. 365-374, 2019.Search in Google Scholar

M. Somashekhar, “Design of a Low Power D-Flip Flop using AVL Technique”, International Journal of Advanced Research in Computer and Communication Engineering, vol. 4(9), pp. 291-293, 2015.Search in Google Scholar

K. Swetha, K. Syamala, and U.M. Godugu, “Design of Low Power D-Flip Flop using True Single Phase Clock”, International Journal & Magazine of Engineering, Technology, Management, and Research, vol. 4(4), pp. 370-374, 2017.Search in Google Scholar

B.S. Premananda, K.J. Nikhil, and H.M. Sumana, “Low-power Square Root Carry Select Adder using AVLS-TSPC-based D Flip-flop”, Electrica Journal, vol. 22(1), pp. 109-118, 2022.Search in Google Scholar

S. Jia, Y. Shilin, W. Yuan, and Z. Ganggang “Low-Power, High-Speed Dual Modulus Pre-scalers Based on Branch-Merged True Single-Phase Clocked Scheme”, Electronics Letters: Ciruits and Systems, vol. 51(6), pp. 464-465, 2015.Search in Google Scholar

F.P.H de Miranda, N.S. Joao, and W.A.M.V. Noije, “A 4 GHz Dual Modulus Divider-by 32/33 Prescaler in 0.35µm CMOS Technology”, 17th Symposium on Integrated Circuits and System Design, pp. 94-99, 2004.Search in Google Scholar

R.A. Dabhi and B.H. Nagpara, “CMOS Low Power, High-Speed Dual Modulus 32/33 Prescaler in sub-nanometer Technology”, International Journal of Science Technology & Engineering, vol. 1(1), pp. 28-32, 2014.Search in Google Scholar

B.S. Premananda, and S. Srivaths, “Low-Power Phase Frequency Detector using Hybrid AVLS and LECTOR Techniques for Low-Power PLL”, Advances in Electrical and Electronic Engineering, vol. 20(3), pp. 294-303, 2022.Search in Google Scholar

B.S. Premananda, N. Sahithi, and Sanya Mittal, “AVLS-based 32/33 Pre-scaler for Frequency Dividers”, e-Prime - Advances in Electrical Engineering, Electronics and Energy, vol. 4, pp. 1-5, 2023.Search in Google Scholar

W.C. Lai, “Fractional-N Frequency Synthesizer for Spread Spectrum Clock Generation Applications”, 9th Asia-Pacific Conference on Antennas and Propagation, pp. 1-6, 2020.Search in Google Scholar

M. Divya Shree, and H. Venkatesh Kumar, “Design of a High Frequency Dual Modulus Prescaler using Efficient TSPC Flip Flop using 180nm Technology”, International Journal of Innovative Research in Science, Engineering and Technology, vol. 4(7), pp. 5485-5492, 2015.Search in Google Scholar

eISSN:
1339-309X
Język:
Angielski
Częstotliwość wydawania:
6 razy w roku
Dziedziny czasopisma:
Engineering, Introductions and Overviews, other