Otwarty dostęp

Analysis of SMT component land pad discontinuity effect on the overall transmission line impedance in high-speed applications


Zacytuj

S. H. Hall, and H. L. Heck, Advanced Signal Integrity for High-Speed Digital Designs, Wiley-IEEE Press, 2009. Search in Google Scholar

Texas Instruments, High-Speed Interface Layout Guidelines, Application Note, https://www.ti.com/lit/an/spraar7i/spraar7i.pdf, 16-Mar-2023. Search in Google Scholar

Toradex, Layout Design Guide, https://docs.toradex.com/102492-layout-design-guide.pdf, 16-Mar-2023. Search in Google Scholar

Renesas, RYZ024A Module Integration Guide, https://www.renesas.com/us/en/document/apn/ryz024a-module-integration-gui de, 16-Mar-2023. Search in Google Scholar

Intel, AN 672, Transceiver Link Design Guidelines for High-Gbps Data Rate, https://www.intel.com/content/www/us/en/programmable/documentation/nik1412632494319.html, Mar-2023. Search in Google Scholar

STMicroelectronics, Introduction Optimized RF board layout for STM32WL Series AN5407, 16-Mar-2023. Search in Google Scholar

L. W. Chew, C. Y. Tan, M. D. Chai, and Y. R. Lim, “PCB Channel Optimization Techniques for High-Speed Differential Interconnects”, International Conference on Electronics Packaging (ICEP), https://doi.org/10.23919/icep55381.2022.9795393, 2022. Search in Google Scholar

Q.T.Lai,J. F.Mao and M.S.Zhang, “Compensation Design for DC Blocking Multilayer Ceramic Capacitor in High-Speed Applications”, IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 5, pp. 742-751, Mayhttps://doi.org/10.1109/TCPMT.2011.2116016, 2011. Search in Google Scholar

M. Vasa, A. C. Reddy, B. Mutnury, S. Kumar, and R. D. Vasanth, “High speed interconnect optimization”, Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC), https://doi.org/10.1109/apemc.2015.7175345, 2015. Search in Google Scholar

K. T. Wu, H. Lin, B. C. Tseng, and J. Yen, “Analysis of Ground Void Patterns for Differential Microstrip Impedance Matching on Surface Mount Pads”, Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC), https://doi.org/10.1109/apemc49932.2021.9597190, 2021. Search in Google Scholar

Z. Vainoris, Bang elektronikos pagrindai: vadovlis, Vilnius: Technika, 2004. Search in Google Scholar

V. Barzdenas, and A. Vasjanov, “A Method of Optimizing Characteristic Impedance Compensation Using Cut-Outs in High-Density PCB Designs”, MDPI Sensors, vol. 22, no. 3, pp. 964 https://doi.org/10.3390/s22030964, 2022. Search in Google Scholar

Y. C. Fei, “Optimized surface mount structure for multi-gigabit transmission”, 2nd International Conference on Electronic Design, ICED, pp. 84-88, https://doi.org/10.1109/ICED.2014.7015776, 2014. Search in Google Scholar

F. Kong, W. Sheng, H. Wang, J. Wu, and M. Xiaofeng, “Signal integrity analysis for highspeed circuit PCB interconnection with an efficient full wave method”, International Journal of RF and Microwave Computer-Aided Engineering, pp. 586-597, https://doi.org/10.1002/mmce.20693, 2022. Search in Google Scholar

eISSN:
1339-309X
Język:
Angielski
Częstotliwość wydawania:
6 razy w roku
Dziedziny czasopisma:
Engineering, Introductions and Overviews, other