<abstract xmlns="http://www.w3.org/1999/xhtml">

<p>This paper deals with the development and experimental verification of a low-power AC/DC converter. The proposed solution is aimed at the sub 0.5 W output power domain, commonly encountered in applications such as always-on wireless sensing nodes. To implement the proposed converter topology, a prototype application specific integrated circuit was designed and manufactured in a high voltage 0.35 µm CMOS technology, able to handle the maximum voltage of up to 120 V. The proposed design was first analyzed by transistor-level simulations showing high power efficiency and low no-load consumption of the developed converter. To facilitate experimental verification and measurement, an printed circuit board with the necessary external components was developed, as the available technology is unable to handle the AC line voltage directly. While the developed converter operated well with decreased input AC voltage, reliability issues arose during operation with the full AC line voltage of 230 Vrms. These are linked to digital control circuitry of the implemented chip and could be addressed in the second manufacturing run in the future.</p>
</abstract>

This paper deals with the development and experimental verification of a low-power AC/DC converter. The proposed solution is aimed at the sub 0.5 W output power domain, commonly encountered in applications such as always-on wireless sensing nodes. To implement the proposed converter topology, a prototype application specific integrated circuit was designed and manufactured in a high voltage 0.35 µm CMOS technology, able to handle the maximum voltage of up to 120 V. The proposed design was first analyzed by transistor-level simulations showing high power efficiency and low no-load consumption of the developed converter. To facilitate experimental verification and measurement, an printed circuit board with the necessary external components was developed, as the available technology is unable to handle the AC line voltage directly. While the developed converter operated well with decreased input AC voltage, reliability issues arose during operation with the full AC line voltage of 230 Vrms. These are linked to digital control circuitry of the implemented chip and could be addressed in the second manufacturing run in the future.

Design and verification of a low-power AC/DC converter

Faculty of Electrical Engineering and Information Technology

Journal of Electrical Engineering

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

{"article-title":"Design and verification of a low-power AC/DC converter"}

This paper deals with the development and experimental verification of a low-power AC/DC converter. The proposed solution is aimed at the sub 0.5 W output...

Design and verification of a low-power AC/DC converter

Data publikacji: 12 maj 2021

Zakres stron: 113 - 118

Otrzymano: 15 lut 2021

DOI: https://doi.org/10.2478/jee-2021-0015

Słowa kluczowe
AC/DC power conversion, CMOS integrated circuits, low-power design, power efficiency, ASIC, sensor nodes

© 2021 Miroslav Potočný et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Design and verification of a low-power AC/DC converter

Data publikacji: 12 maj 2021

Zakres stron: 113 - 118

Otrzymano: 15 lut 2021

DOI: https://doi.org/10.2478/jee-2021-0015

Słowa kluczoweAC/DC power conversion, CMOS integrated circuits, low-power design, power efficiency, ASIC, sensor nodes

© 2021 Miroslav Potočný et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Słowa kluczowe
AC/DC power conversion, CMOS integrated circuits, low-power design, power efficiency, ASIC, sensor nodes