<abstract xmlns="http://www.w3.org/1999/xhtml"><p> This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (−0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.</p></abstract>

This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (−0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Department of Electrical and Electronics Engineering, Abant Izzet Baysal University, Golkoy Campus, Bolu, Turkey

Journal of Electrical Engineering

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel...

Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Data publikacji: 10 lis 2015

Zakres stron: 250 - 256

Otrzymano: 30 cze 2015

DOI: https://doi.org/10.2478/jee-2015-0041

Słowa kluczowe
fully parallel A/D converter, common gate differential MOS pair, transmission gate based multiplexer circuit, high speed A/D converter

© Faculty of Electrical Engineering and Information Technology, Slovak University of Technology

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Data publikacji: 10 lis 2015

Zakres stron: 250 - 256

Otrzymano: 30 cze 2015

DOI: https://doi.org/10.2478/jee-2015-0041

Słowa kluczowefully parallel A/D converter, common gate differential MOS pair, transmission gate based multiplexer circuit, high speed A/D converter

© Faculty of Electrical Engineering and Information Technology, Slovak University of Technology

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Słowa kluczowe
fully parallel A/D converter, common gate differential MOS pair, transmission gate based multiplexer circuit, high speed A/D converter