Towards a design space exploration methodology for system-on-chip

Data publikacji: 09 kwi 2014

Zakres stron: 101 - 111

DOI: https://doi.org/10.2478/cait-2014-0008

Słowa kluczowe

System-on-Chip, On-chip interconnect, simulation, performance evaluation, design-space exploration

© by A. Chariete

This article is distributed under the terms of the Creative Commons Attribution Non-Commercial License, which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.