<abstract xmlns="http://www.w3.org/1999/xhtml">

<p>This paper describes the hardware implementation methodologies of fixed point binary division algorithms. The implementations have been extended for the execution of the reciprocal of the binary numbers. Radix-2 (binary) implementations of digit recurrence and multiplicative based methods have been considered for comparison. Functionality of the algorithms have been verified in Verilog hardware description language (HDL) and synthesized in Xilinx ISE 8.2i targeting the device xc4vlx15-12sf363 of Virtex4 family. Implementation was done for both signed and unsigned number systems, having bit width of operands vary as an exponential function of 2<sup>n</sup>, where n=2 to 5. Performance parameters have been calculated in terms of clock frequency, FPGA slice utilization, latency and power consumption. Implementation results indicate that multiplicative based algorithm is superior in terms of latency, while digit recurrence algorithms are consuming low power along-with less area overhead.</p>
</abstract>

This paper describes the hardware implementation methodologies of fixed point binary division algorithms. The implementations have been extended for the execution of the reciprocal of the binary numbers. Radix-2 (binary) implementations of digit recurrence and multiplicative based methods have been considered for comparison. Functionality of the algorithms have been verified in Verilog hardware description language (HDL) and synthesized in Xilinx ISE 8.2i targeting the device xc4vlx15-12sf363 of Virtex4 family. Implementation was done for both signed and unsigned number systems, having bit width of operands vary as an exponential function of 2n, where n=2 to 5. Performance parameters have been calculated in terms of clock frequency, FPGA slice utilization, latency and power consumption. Implementation results indicate that multiplicative based algorithm is superior in terms of latency, while digit recurrence algorithms are consuming low power along-with less area overhead.

HARDWARE IMPLEMENTATION OF METHODOLOGIES OF FIXED POINT DIVISION ALGORITHMS

International Journal on Smart Sensing and Intelligent Systems

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

{"article-title":"HARDWARE IMPLEMENTATION OF METHODOLOGIES OF FIXED POINT DIVISION ALGORITHMS"}

This paper describes the hardware implementation methodologies of fixed point binary division algorithms. The implementations have been extended for the...

HARDWARE IMPLEMENTATION OF METHODOLOGIES OF FIXED POINT DIVISION ALGORITHMS

Data publikacji: 01 mar 2017

Zakres stron: 1 - 16

Otrzymano: 28 maj 2017

Przyjęty: 24 lip 2017

DOI: https://doi.org/10.21307/ijssis-2017-227

Słowa kluczowe
Digit recurrence, Division algorithm, Fixed point, FPGA, Newton-Raphson, Verilog

© 2017 D. Kumar et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

HARDWARE IMPLEMENTATION OF METHODOLOGIES OF FIXED POINT DIVISION ALGORITHMS

Data publikacji: 01 mar 2017

Zakres stron: 1 - 16

Otrzymano: 28 maj 2017

Przyjęty: 24 lip 2017

DOI: https://doi.org/10.21307/ijssis-2017-227

Słowa kluczoweDigit recurrence, Division algorithm, Fixed point, FPGA, Newton-Raphson, Verilog

© 2017 D. Kumar et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Słowa kluczowe
Digit recurrence, Division algorithm, Fixed point, FPGA, Newton-Raphson, Verilog