<abstract xmlns="http://www.w3.org/1999/xhtml"><p>As transistors become increasingly smaller and faster and noise margins become tighter, circuits and chip specially microprocessors tend to become more vulnerable to permanent and transient hardware faults. Most microprocessor designers focus on protecting memory elements among other parts of microprocessors against hardware faults through adding redundant error-correcting bits such as parity bits. How ever, the rate of soft errors in combinational parts of microprocessors is consider edas important as in sequential parts such as memory elements nowadays. The reason is that advances in scaling technology have led to reduced electrical masking .This paper proposes and evaluates a logic level fault-tolerant method based on parity for designing combinational circuits. Experimental results on a full adder circuit show that the proposed method makes the circuit fault-tolerant with less overhead in comparison with traditional methods. It will also be demonstrated that our proposed method enables the traditional TMR method to detect multiple faults in addition to single fault masking.</p></abstract>

As transistors become increasingly smaller and faster and noise margins become tighter, circuits and chip specially microprocessors tend to become more vulnerable to permanent and transient hardware faults. Most microprocessor designers focus on protecting memory elements among other parts of microprocessors against hardware faults through adding redundant error-correcting bits such as parity bits. How ever, the rate of soft errors in combinational parts of microprocessors is consider edas important as in sequential parts such as memory elements nowadays. The reason is that advances in scaling technology have led to reduced electrical masking .This paper proposes and evaluates a logic level fault-tolerant method based on parity for designing combinational circuits. Experimental results on a full adder circuit show that the proposed method makes the circuit fault-tolerant with less overhead in comparison with traditional methods. It will also be demonstrated that our proposed method enables the traditional TMR method to detect multiple faults in addition to single fault masking.

A Fault Detection Method for Combinational Circuits

International Journal of Advanced Network, Monitoring and Controls

This work is licensed under the Creative Commons Attribution 4.0 International License.

{"article-title":"A Fault Detection Method for Combinational Circuits"}

As transistors become increasingly smaller and faster and noise margins become tighter, circuits and chip specially microprocessors tend to become more...

A Fault Detection Method for Combinational Circuits

Data publikacji: 01 kwi 2018

Zakres stron: 1 - 5

DOI: https://doi.org/10.21307/ijanmc-2016-004

Słowa kluczowe
Soft Error, Transient Fault, Fault-Tolerance, Combinational Circuits, Full Adder

© 2016 AliAbbass Zoraghchian et al., published by Sciendo

This work is licensed under the Creative Commons Attribution 4.0 International License.

A Fault Detection Method for Combinational Circuits

Data publikacji: 01 kwi 2018

Zakres stron: 1 - 5

DOI: https://doi.org/10.21307/ijanmc-2016-004

Słowa kluczoweSoft Error, Transient Fault, Fault-Tolerance, Combinational Circuits, Full Adder

© 2016 AliAbbass Zoraghchian et al., published by Sciendo

This work is licensed under the Creative Commons Attribution 4.0 International License.

Słowa kluczowe
Soft Error, Transient Fault, Fault-Tolerance, Combinational Circuits, Full Adder