<abstract xmlns="http://www.w3.org/1999/xhtml"><p> The paper is dedicated to parallel data sort based on sorting networks. The proposed methods and circuits have the following characteristics: 1) using two-level parallel comparators in even-odd transition networks with feedback to a register keeping input/intermediate data; 2) parallel merging of many sorted sequences; 3) using even-odd transition networks built from other sorting networks; 4) rational reuse of comparators in different types of networks, namely even-odd transition and for discovering maximum/minimum values. The experiments in FPGA, which were done for up to 16×2<sup>20</sup> 32-bit data items, demonstrate very good results (as fast as 3-5 ns per data item).</p></abstract>

The paper is dedicated to parallel data sort based on sorting networks. The proposed methods and circuits have the following characteristics: 1) using two-level parallel comparators in even-odd transition networks with feedback to a register keeping input/intermediate data; 2) parallel merging of many sorted sequences; 3) using even-odd transition networks built from other sorting networks; 4) rational reuse of comparators in different types of networks, namely even-odd transition and for discovering maximum/minimum values. The experiments in FPGA, which were done for up to 16×220 32-bit data items, demonstrate very good results (as fast as 3-5 ns per data item).

FPGA-based Accelerators for Parallel Data Sort

Tallinn University of Technology, Estonia

Applied Computer Systems

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

{"article-title":"FPGA-based Accelerators for Parallel Data Sort"}

The paper is dedicated to parallel data sort based on sorting networks. The proposed methods and circuits have the following characteristics: 1) using...

FPGA-based Accelerators for Parallel Data Sort

Data publikacji: 27 sty 2015

Zakres stron: 53 - 63

DOI: https://doi.org/10.1515/acss-2014-0013

Słowa kluczowe
Merging, performance analysis reconfigurable architectures, sorting

© Riga Technical University

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

FPGA-based Accelerators for Parallel Data Sort

Data publikacji: 27 sty 2015

Zakres stron: 53 - 63

DOI: https://doi.org/10.1515/acss-2014-0013

Słowa kluczoweMerging, performance analysis reconfigurable architectures, sorting

© Riga Technical University

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Słowa kluczowe
Merging, performance analysis reconfigurable architectures, sorting