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A Multi–Alphabet Arithmetic Coding Hardware Implementation for Small FPGA Devices

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Arithmetic coding is a lossless compression algorithm with variable-length source coding. It is more flexible and efficient than the well-known Huffman coding. In this paper we present a non-adaptive FPGA implementation of a multi-alphabet arithmetic coding with separated statistical model of the data source. The alphabet of the data source is a 256-symbol ASCII character set and does not include the special end-of-file symbol. No context switching is used in the proposed design which gives maximal throughput without pipelining. We have synthesized the design for Xilinx FPGA devices and used their built-in hardware resources.

ISSN:
1335-3632
Lingua:
Inglese
Frequenza di pubblicazione:
6 volte all'anno
Argomenti della rivista:
Engineering, Introductions and Overviews, other