<abstract xmlns="http://www.w3.org/1999/xhtml">

<p>One of the remarkable issues that face wireless sensor networks (WSNs) nowadays is security. WSNs should provide a way to transfer data securely particularly when employed for mission-critical purposes. In this paper, we propose an enhanced architecture and implementation for 128-bit Schmidt-Samoa cryptosystem (SSC) to secure the data communication for wireless sensor networks (WSN) against external attacks. The proposed SSC cryptosystem has been efficiently implemented and verified using FPGA modules by exploiting the maximum allowable parallelism of the SSC internal operations. To verify the proposed SSC implementation, we have synthesized our VHDL coding using Quartus II CAD tool targeting the Altera Cyclone IV FPGA EP4CGX22CF19C7 device. Hence, the synthesizer results reveal that the proposed cryptographic FPGA processor recorded an attractive result in terms of critical path delay, hardware utilization, maximum operational frequency FPGA thermal power dissipation for low-power applications such as the wireless sensor networks.</p>
</abstract>

One of the remarkable issues that face wireless sensor networks (WSNs) nowadays is security. WSNs should provide a way to transfer data securely particularly when employed for mission-critical purposes. In this paper, we propose an enhanced architecture and implementation for 128-bit Schmidt-Samoa cryptosystem (SSC) to secure the data communication for wireless sensor networks (WSN) against external attacks. The proposed SSC cryptosystem has been efficiently implemented and verified using FPGA modules by exploiting the maximum allowable parallelism of the SSC internal operations. To verify the proposed SSC implementation, we have synthesized our VHDL coding using Quartus II CAD tool targeting the Altera Cyclone IV FPGA EP4CGX22CF19C7 device. Hence, the synthesizer results reveal that the proposed cryptographic FPGA processor recorded an attractive result in terms of critical path delay, hardware utilization, maximum operational frequency FPGA thermal power dissipation for low-power applications such as the wireless sensor networks.

Implementing a lightweight Schmidt-Samoa cryptosystem (SSC) for sensory communications

International Journal on Smart Sensing and Intelligent Systems

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

running-head

One of the remarkable issues that face wireless sensor networks (WSNs) nowadays is security. WSNs should provide a way to transfer data securely particularly...

Design area analysis	The number of logic elements (LEs)	58,719 LEs
	The number of four-input look-up table	234,876 LUTs
	The number of registers	29,883
	Memory utilization	50%
	Total number of I/O pins	389
	I/O utilization	76%
Design timing analysis	Total path delay for critical clock cycle	25.02 ns
	Maximum frequency	40 MHz
	Critical clock cycles to perform SSC process	5 million clocks
	Total processing delay to perform SSC process	125 ms
Design power analysis	Dynamic thermal power dissipation (I/O assignments and operations)	102.6 mW
	Static thermal power dissipation	148.7 mW
	Total FPGA thermal power dissipation	251.3 mW

Implementing a lightweight Schmidt-Samoa cryptosystem (SSC) for sensory communications

Article Category: research-article

Pubblicato online: 27 ago 2019

Pagine: 1 - 9

Ricevuto: 12 mag 2019

DOI: https://doi.org/10.21307/ijssis-2019-006

Parole chiave
Cryptography, Computer arithmetic, Schmidt-Samoa Cryptosystem, Wireless sensors

© 2019 Qasem Abu Al-Haija et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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Figure 7:

Cost factor analysis for the FPGA design of 128-bit SSC Cryptoprocessor.

Implementing a lightweight Schmidt-Samoa cryptosystem (SSC) for sensory communications

Article Category: research-article

Pubblicato online: 27 ago 2019

Pagine: 1 - 9

Ricevuto: 12 mag 2019

DOI: https://doi.org/10.21307/ijssis-2019-006

Parole chiaveCryptography, Computer arithmetic, Schmidt-Samoa Cryptosystem, Wireless sensors

© 2019 Qasem Abu Al-Haija et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Figure 1:

Figure 2:

Figure 3:

Figure 4:

Figure 5:

Figure 6:

Figure 7:

Cost factor analysis for the FPGA design of 128-bit SSC Cryptoprocessor.

Parole chiave
Cryptography, Computer arithmetic, Schmidt-Samoa Cryptosystem, Wireless sensors