Implementing a lightweight Schmidt-Samoa cryptosystem (SSC) for sensory communications
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27 ago 2019
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Categoría del artículo: research-article
Publicado en línea: 27 ago 2019
Páginas: 1 - 9
Recibido: 12 may 2019
DOI: https://doi.org/10.21307/ijssis-2019-006
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© 2019 Qasem Abu Al-Haija et al., published by Sciendo
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
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Cost factor analysis for the FPGA design of 128-bit SSC Cryptoprocessor_
| Design area analysis | The number of logic elements (LEs) | 58,719 LEs |
|---|---|---|
| The number of four-input look-up table | 234,876 LUTs | |
| The number of registers | 29,883 | |
| Memory utilization | 50% | |
| Total number of I/O pins | 389 | |
| I/O utilization | 76% | |
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| Maximum frequency | 40 MHz | |
| Critical clock cycles to perform SSC process | 5 million clocks | |
| Total processing delay to perform SSC process | 125 ms | |
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| Static thermal power dissipation | 148.7 mW | |
| Total FPGA thermal power dissipation | 251.3 mW |