Time-dependent gate breakdown reliability and gate leakage improvements in p-GaN MOS-HEMTs using Al₂O₃ gate dielectric

Gallium nitride (GaN), characterized by its wide bandgap and high-electron mobility, has become a standout material in the field of power devices [1,2,3]. Devices made using AlGaN/GaN high-electron mobility transistors (HEMTs) demonstrate a remarkable ability to reduce energy consumption during high-power operation [4,5]. By adopting a p-GaN gate structure, enhancement-mode (E-mode) device operation can be achieved, enabling extremely high conversion efficiency and further delivering high power density [6]. Its key advantage lies in providing better controllability during the epitaxial process compared to other approaches. This approach also represents one of the most commercially viable technologies available today [7]. However, a significant challenge associated with this technology is the ON-state gate time-dependent dielectric breakdown, which occurs when the gate-source voltage is high and sustained for a sufficiently long duration, leading to leakage issues [8,9,10,11,12]. This also tests the durability and reliability of E-mode p-GaN HEMTs. One potential solution to address this issue is to add an insulating layer on the p-GaN gate, and this modification can increase the threshold voltage (V _th) and reduce gate leakage [13,14,15]. Al₂O₃ was selected as the gate dielectric material due to its wide bandgap, high thermal stability, and excellent interface quality with GaN, which are critical for suppressing gate leakage and enhancing device reliability [16,17].

In previous studies, it has been shown that the residual p-GaN outside the gate region must be etched only after removing the oxide layer. To achieve this, conventional approaches often utilize inductively coupled plasma reactive ion etching (ICP-RIE) techniques [13,18,19]. Additionally, the transfer length method (TLM) has been widely employed to extract contact and sheet resistances, serving as an effective means to validate the formation of reliable source/drain ohmic contacts and to confirm the presence of a two-dimensional electron gas (2DEG) within the channel region [20].

In this work, we propose two process improvements for p-GaN gate-based E-mode HEMTs. First, we develop a self-aligned two-step etching process using two consecutive ICP-RIE recipes to separately remove the oxide and residual p-GaN layers outside the gate region, thus eliminating the need for an additional mask. Second, we assess the feasibility of this etching process by extracting the device’s contact and sheet resistance via TLM. Furthermore, we deposit a 10 nm Al₂O₃ layer on the p-GaN using thermal atomic layer deposition (ALD) to fabricate a metal–oxide–semiconductor high-electron mobility transistor (MOS-HEMT) structure and compare its performance to that of a conventional p-GaN gate HEMT with an ohmic gate contact. To further evaluate the long-term reliability of the gate dielectric, we also perform time-dependent gate breakdown (TDGB) measurements [9,21]. Finally, the role of post-deposition annealing (PDA) in enhancing MOS-HEMT performance was investigated by comparing the DC characteristics and TDGB lifetime of devices with and without PDA treatment.

The HEMTs we fabricated are based on a commercial GaN-on-Si substrate. This substrate is formed by heteroepitaxially growing an AlGaN/GaN structure on a 6-in. (111) silicon wafer using metal-organic chemical vapor deposition. It consists of a 1 μm carbon-doped GaN buffer layer, a 300 nm channel layer, a 1 nm AlN spacer layer, a 12.5 nm AlGaN barrier layer, and a 100 nm p-GaN layer. The fabrication process of the standard p-GaN gate HEMT with an ohmic-gate contact (Figure 1(a)) involves several steps. First, mesa isolation is performed using ICP-RIE. Next, the 100 nm p-GaN layer above the source and drain regions is removed by ICP-RIE. Following this, source/drain ohmic contacts are formed with a Ti/Al/Ti/Au (25/125/45/90 nm) metal stack, which is deposited and then annealed at 800°C for 1 min using a rapid thermal annealing system. The source-to-drain spacing (L _SD) is 10 μm. Subsequently, the gate metal, consisting of a Ni/Au (45/90 nm) stack, is deposited to act as a hard mask for further etching. The gate length (L _G) is 2 μm, and the gate width (W _G) is 100 μm. The residual p-GaN layer in regions outside the three electrodes is then etched using ICP-RIE to complete the device fabrication process. In addition to the standard ohmic gate contact device, we also fabricated another type of device, an MOS-HEMT (Figure 1(b)), which features an oxide layer between the gate metal and the p-GaN layer. The key difference lies in the fabrication process following the completion of the source/drain ohmic contacts. A 10 nm layer of Al₂O₃ was deposited using thermal ALD at 300°C. After ALD, PDA was performed at 600°C for 10 min in N₂ ambient to smoothen the oxide/p-GaN interface. To verify the necessity of the PDA process, we also fabricated an MOS-HEMT without PDA and measured its characteristics as a reference. Following patterning the gate, a two-step etching process was performed using different ICP recipes. In the first step, the Al₂O₃ layer was etched, followed by etching of the remaining p-GaN layer to complete the device fabrication process. Traditionally, Al₂O₃ is removed using HF wet etching, but this isotropic process often leads to imprecise linewidth control and potential contamination issues. In contrast, ICP anisotropic etching allows for much more precise linewidth control, effectively addressing these problems. This approach is particularly advantageous for the future development of MOS-HEMTs with smaller gate linewidths. By adopting this method, one not only avoids the drawbacks associated with HF etching but also provides a more reliable fabrication process for improved device performance.

Figure 1

Schematic cross-sectional structure of the (a) p-GaN gate HEMT with ohmic gate contact and (b) the MOS-HEMT.

The residual p-GaN etching is difficult and critical to the entire HEMT process [19,22]. To address this, we developed a Cl₂/O₂/Ar etching recipe with a selectivity of about 1:10 between AlGaN and p-GaN. This selectivity allowed the AlGaN barrier to act as an etch-stop layer. As shown in Figure 2, the selective etching forms an oxidation layer on the AlGaN, preventing further etching. This etching recipe ensures that we achieve the expected device performance. We will also verify the sheet resistance in the access region of our device through TLM to ensure it is sufficiently low, confirming the successful completion of the etching process.

Figure 2

Cross-sectional TEM image of an over-etched substrate (containing oxidized [white]) and residual [light gray] AlGaN) by selective etching between p-GaN and AlGaN (top) and element distribution in the over-etched substrate generated from the EDS line scan (bottom).

Figure 3(a)–(c) shows the resistance of the p-GaN gate HEMT with ohmic gate contact and the MOS-HEMTs before and after PDA treatment, which are analyzed using the TLM pattern. The top-view image of the TLM pattern is shown in the inset of Figure 3(a). The results indicate that our devices have a reasonable ohmic contact on source/drain, with contact resistance (R _C) all below 5 Ω·mm and a low specific contact resistivity (ρ _C). Additionally, the low sheet resistance (R _sh) of ∼1 kΩ/sq suggests that the access region has a high-density 2DEG, which was not diminished by our residual p-GaN etching process [23]. The consistency of the TLM results confirms that the MOS process does not affect the performance of the ungated region.

Figure 3

TLM results of (a) the p-GaN gate HEMT with ohmic gate contact and the MOS-HEMTs (b) before and (c) after PDA treatment.

Figure 4(a)–(c) shows the I–V characteristics of the p-GaN gate HEMT with an ohmic gate contact. Specifically, Figure 4(a) demonstrates a V _th of 0.81 V and a subthreshold swing (SS) of 75.61 mV/dec. These results indicate that our standard ohmic gate device not only exhibits E-mode characteristics but also demonstrates excellent gate control. Notably, even without the assistance of an insulating layer structure, a remarkably low gate current of ∼10⁻⁷ mA/mm is achieved. Additionally, Figure 4(b) shows a drain current of ∼300 mA/mm, a maximum transconductance (g _{m, max}) of 76.64 mS/mm, and a field-effect mobility of 684 cm²/V s. Figure 4(c) presents the output characteristics, with a maximum drain current (I _D,max) of 350 mA/mm and a moderate ON-state resistance (R _ON) of 12.5 Ω mm at V _GS = 10 V. These superior characteristics are primarily attributed to two key factors: the effective preservation of the high-electron mobility 2DEG conduction channel beneath the remaining p-GaN layer during ICP selective etching and the adoption of ohmic contact source/drain metal. TLM measurements demonstrate low sheet resistance and contact resistance, further contributing to the excellent performance.

Figure 4

(a) Transfer characteristics of the HEMT with ohmic gate contact in linear scale: the left Y-axis shows the drain current, and the right Y-axis shows the transconductance. (b) Transfer characteristics in logarithmic scale: the left Y-axis shows the drain current, and the right Y-axis shows the gate leakage current. (c) Output characteristics of the device under different gate voltages.

Figure 5(a) and (b) shows the I–V characteristics of transfer characteristics among the three types of HEMTs. Without PDA treatment, the MOS-HEMT shows degraded electrical characteristics compared to conventional HEMTs with ohmic gate contact. Notably, the OFF-state current of MOS-HEMT is higher than that of the conventional HEMT with an ohmic gate contact. This is due to the poor interface bonding between oxide and p-GaN, which facilitates the easier injection of carriers from the gate into the channel. Additionally, it increases the overall effective oxide thickness (i.e., the distance from the gate to the channel). In other words, the equivalent gate capacitance is reduced, resulting in a decreased amount of electrons that the gate can attract; therefore, the drain current should tend to decrease [24]. As a result, the MOS-HEMT exhibits higher OFF-state current, poorer SS, and lower ON-state current. On the contrary, PDA treatment effectively improves the interface characteristics, reducing interface defects and stabilizing the device’s performance. This leads to a significant reduction in the OFF current and a notable improvement in the SS, which enhances the gate control over the channel. However, PDA also significantly reduces interface states between oxide and p-GaN, which, although beneficial for device stability, has the unintended effect of lowering the available carrier concentration in the channel. Donor-like interface states above the AlGaN layer serve as a primary source of additional carriers in GaN materials, and their reduction decreases the channel’s carrier concentration [25,26,27]. Given the inherently low intrinsic carrier concentration in GaN, this directly results in a further reduction in the ON-state current. Table 1 summarizes the comparison of typical performance parameters among the three types of HEMTs.

Figure 5

(a) Comparison of transfer characteristics among the three types of HEMTs in a log scale and (b) in a linear scale.

We explored the effects of these three structures through the I _G –V _G curve shown in Figure 6. First, it can be observed that the OFF-state current of HEMTs is closely related to their respective reverse gate leakage levels. Additionally, the HEMTs with ohmic gate contacts exhibit two slope peaks during the turn-on process, which are attributed to the hole injection effect commonly seen in p-GaN gate HEMTs [7]. In contrast, this phenomenon is absent in MOS-HEMTs because the gate insulator effectively blocks hole injection. Comparing the ON-state current among the three types, it is evident that the ohmic gate HEMTs experience a significant current increase due to the hole injection effect, which further enhances I _D,max. On the contrary, MOS-HEMTs effectively suppress the sudden rise in forward gate leakage, maintaining a safer current level. Finally, when comparing MOS-HEMTs before and after PDA treatment, MOS-HEMTs with PDA can reduce reverse gate current to an ultra-low leakage level below that of the standard ohmic gate HEMTs. At the same time, they provide a more stable and smoother ON-state current curve.

Figure 6

Comparison of I _G–V _G characteristics among the three types of HEMTs.

To further compare the impact of PDA on gate reliability in MOS-HEMTs, we performed TDGB tests. A constant gate voltage was applied while the source and drain electrodes were grounded, as illustrated in Figure 7(a)–(f). The breakdown time (t _BD) is defined as the moment when the gate leakage current abruptly increases to 10² mA/mm. From Figure 7(a) and (d), it is evident that MOS-HEMTs with PDA improved forward gate leakage characteristics, showing consistently lower leakage current compared to devices without PDA. The Weibull distribution is used to model the TDGB behavior of the devices and is expressed as (1) ln ( − ln ( 1 − F ( t BD ) ) ) = β ln t BD − β ln η , \mathrm{ln}(-\mathrm{ln}(1-F({t}_{{\rm{BD}}})))=\beta \mathrm{ln}{t}_{{\rm{BD}}}-\beta \mathrm{ln}\eta , where F(t _BD) represents the probability of failure occurring at a given t _BD, β is the shape factor, and η is the scale factor. The Weibull plots in Figure 7(b) and (e), which show ln(−ln(1 − F(t))) versus t _BD, indicate that the time-to-failure follows a Weibull distribution. Notably, MOS-HEMTs with PDA exhibit a relatively higher shape factor β and a longer lifetime distribution, indicating improved reliability. In the plots of t _BD versus V _G (Figure 7(c) and (f)), fitted using an exponential model, the maximum gate voltage that ensures a 10-year lifetime at room temperature with a 1% failure rate is estimated to be 7.2 V for MOS-HEMTs with PDA. This represents a significant improvement in lifetime compared to the poor reliability observed in devices without PDA. These results confirm the enhanced forward gate robustness of p-GaN gate MOS-HEMTs after PDA treatment. Table 2 compares the switching performance of our device with other reported E-mode GaN-based devices. Our MOS-HEMT exhibits competitive advantages, particularly in gate leakage suppression and enhancement-mode operation, demonstrating the effectiveness of the Al₂O₃ layer and PDA treatment.

Figure 7

TDGB of MOS-HEMTs without (a) and with (d) PDA, Weibull plots of MOS-HEMTs without (b) and with (e) PDA, and lifetime predictions of MOS-HEMTs without (c) and with (f) PDA.

In this work, the E-mode p-GaN gate HEMT with ohmic gate contact exhibits excellent electrical performance, including a V _th of 0.81 V, a field-effect mobility of 684 cm²/V s, a maximum drain current of 363 mA/mm, and a high I _ON/I _OFF, while maintaining an ON-state resistance comparable to D-mode devices. These superior characteristics result from the effective preservation of the 2DEG channel during ICP selective etching and appropriate ohmic source/drain metal contact. However, without PDA treatment, MOS-HEMTs suffer from poor oxide/p-GaN interface bonding and reduced effective oxide capacitance, leading to higher OFF-state current, poorer SS, and lower ON-state current compared to conventional p-GaN gate HEMTs with ohmic gate contact. PDA treatment improves interface properties, thereby improving SS and decreasing the OFF-state current. However, it also reduces the interface states of oxide/p-GaN, which lowers the available carrier concentration in the channel. Given GaN’s inherently low intrinsic carrier concentration, this reduction in surface states further decreases the ON current, resulting in a trade-off between improved stability and reduced ON-state performance. To further validate the effect of PDA, TDGB experiments reveal that MOS-HEMTs with PDA exhibit lower forward gate leakage and longer lifetimes. Weibull analysis confirms improved gate reliability, with a higher shape factor and extended lifetime distribution. Notably, a 10-year lifetime at 7.2 V gate bias is achievable with PDA, highlighting its effectiveness in enhancing gate robustness.

This work was supported by the National Science and Technology Council under the contract number NSTC 113-2221-E-992-110.

This work was supported by the National Science and Technology Council under contract number NSTC 113-2221-E-992-110.

Tsung-I Liao was responsible for the Writing–original draft, Formal analysis, and Data curation. Sheng-Po Chang contributed to Writing–review & editing, Resources, Methodology, Investigation, Funding acquisition, Data curation, and Conceptualization. Shoou-Jinn Chang contributed to Supervision, Project administration, and Conceptualization. All authors reviewed and approved the final version of the manuscript.

The authors declare that they have no conflict of interest.

All authors participated in (a) conception and design or analysis and interpretation of the data; (b) drafting the article or revising it critically for important intellectual content; and (c) approval of the final version.

All authors have seen and approved the final version of the manuscript being submitted. The manuscript is the original work of the authors. All the authors mutually agree to submit to the journal. It is not being submitted elsewhere.

All data generated or analyzed during this study are included in this published article.