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Bandwidth and Common Mode Optimization for Current and Voltage Sources in Bioimpedance Spectroscopy


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Figure 1

Circuitry of a symmetrical Enhanced Howland Current Source, adapted from [8]. The typical EHCS consists of R1 to R4 and Rx, The symmetric signal is generated by the negative output of OP1 over Rt, R5 mimics the current flowing through R1 and R3, The capacitor Cc increases the bandwidth of the current source.
Circuitry of a symmetrical Enhanced Howland Current Source, adapted from [8]. The typical EHCS consists of R1 to R4 and Rx, The symmetric signal is generated by the negative output of OP1 over Rt, R5 mimics the current flowing through R1 and R3, The capacitor Cc increases the bandwidth of the current source.

Figure 2

Theoretical EHCS output impedance for Rx = 1 k, 1.9 kΩ and 4.3 kΩ over R3, Zout(R3,Rx = const) shows asymptotic behavior. Larger Rx require bigger R3 to maximize the possible Zout.
Theoretical EHCS output impedance for Rx = 1 k, 1.9 kΩ and 4.3 kΩ over R3, Zout(R3,Rx = const) shows asymptotic behavior. Larger Rx require bigger R3 to maximize the possible Zout.

Figure 3

Circuit of a VS for BIS measurements, based on the non-inverting amplifier with additional current sense resistor Rs in the feedback loop. Its purpose is to limit the maximum current through Zload, Uout is calculated identically to the output voltage of a non-inverting amplifier.
Circuit of a VS for BIS measurements, based on the non-inverting amplifier with additional current sense resistor Rs in the feedback loop. Its purpose is to limit the maximum current through Zload, Uout is calculated identically to the output voltage of a non-inverting amplifier.

Figure 4

The symmetric input signal of the two VSs (of Figure 3) is generated by the fully differential amplifier OA2, The output signals, running in 180° phase reversal, control two single-ended VSs driving the Zload.
The symmetric input signal of the two VSs (of Figure 3) is generated by the fully differential amplifier OA2, The output signals, running in 180° phase reversal, control two single-ended VSs driving the Zload.

Figure 5

The active offset compensation circuit sums up UL+, UL- and an adjustable Uoffset, The common-mode signal is fed back over a 1st order low pass filter to the Uocm input of the source.
The active offset compensation circuit sums up UL+, UL- and an adjustable Uoffset, The common-mode signal is fed back over a 1st order low pass filter to the Uocm input of the source.

Figure 6

The current of both sources is differentially measured with a shunt resistor. Besides, the output impedance is determined through the voltage drop over the connected load impedances Z1,Z2.
The current of both sources is differentially measured with a shunt resistor. Besides, the output impedance is determined through the voltage drop over the connected load impedances Z1,Z2.

Figure 7

Simulative output impedance of the EHCS with 0.1% resitor tolerances for various Cc. Zout increases with Cc ≤ 2.1 pF for higher frequencies. Higher values of Cc reduces the bandwidth of the EHCS.
Simulative output impedance of the EHCS with 0.1% resitor tolerances for various Cc. Zout increases with Cc ≤ 2.1 pF for higher frequencies. Higher values of Cc reduces the bandwidth of the EHCS.

Figure 8

Simulative output impedance of the symmetrical VS for various Cv. The additional capacitance Cv stabilizes the magnitude of the output impedance above 100 kHz. For even higher values (Cv > 1 nF), the output impedance stays below a few hundred mΩ.
Simulative output impedance of the symmetrical VS for various Cv. The additional capacitance Cv stabilizes the magnitude of the output impedance above 100 kHz. For even higher values (Cv > 1 nF), the output impedance stays below a few hundred mΩ.

Figure 9

Measured output impedance of the symmetrical EHCS for different values of Cc . Between 1 kHz and 50 kHz, the output impedance is for all values of Cc in the range of 100 - 200 kΩ, After 100 kHz, the impedance drops for all measurements just below 10 kΩ.
Measured output impedance of the symmetrical EHCS for different values of Cc . Between 1 kHz and 50 kHz, the output impedance is for all values of Cc in the range of 100 - 200 kΩ, After 100 kHz, the impedance drops for all measurements just below 10 kΩ.

Figure 10

Output current of the EHCS measured for load values in the range of the theoretical maximum operable load 3.5 kΩ, Loads above of 2.47 kΩ experience a significant drop in magnitude (rms value, solid line) and phase (dashed line).
Output current of the EHCS measured for load values in the range of the theoretical maximum operable load 3.5 kΩ, Loads above of 2.47 kΩ experience a significant drop in magnitude (rms value, solid line) and phase (dashed line).

Figure 11

Measured output impedance of the balanced VS with Cv = 82 pF.
Measured output impedance of the balanced VS with Cv = 82 pF.

Figure 12

The output voltage (RMS value, solid line) of the VS were measured for loads in the critical lower load range. Rload = 270 − 740Ω, The phase is depicted as dashed lines.
The output voltage (RMS value, solid line) of the VS were measured for loads in the critical lower load range. Rload = 270 − 740Ω, The phase is depicted as dashed lines.

Figure 13

CMR of the EHCS: The static compensation (green) has a performance loss above 100 kHz, where active compensation (red) and combined compensation (yellow) achieve a more constant CMR over the whole frequency range.
CMR of the EHCS: The static compensation (green) has a performance loss above 100 kHz, where active compensation (red) and combined compensation (yellow) achieve a more constant CMR over the whole frequency range.

Figure 14

CMR of the VS: The static compensation (green) has a performance loss between 10 kHz and 100 kHz, where active compensation (red) and combined compensation (yellow) achieve a more constant CMR over the whole frequency range.
CMR of the VS: The static compensation (green) has a performance loss between 10 kHz and 100 kHz, where active compensation (red) and combined compensation (yellow) achieve a more constant CMR over the whole frequency range.

Figure 15

The second harmonic distortions (solid lines) increase above 100 kHz up to approx. -30 dBc for both sources. In contrast, the third (HD3, dashed lines) harmonic distortions does not show a frequency dependent behavior.
The second harmonic distortions (solid lines) increase above 100 kHz up to approx. -30 dBc for both sources. In contrast, the third (HD3, dashed lines) harmonic distortions does not show a frequency dependent behavior.

The mean CMR without, with static and active compensation methods. The variances σ of the VS (Cv = 82 pF) and current source (Cc = 2.6 pF) are given for the frequency range 1 kHz to 1 MHz.

Compensation Ucm,VS mean [dB] σ Ucm,EHCS mean [dB] σ
Off -29.76 0 -30.71 0
Static -79.04 0.004 -130.08 9.03
Active -39.43 0 -38.65 0.04
Active & Static -128.93 0.5 -139.76 10.91

SNR and THD of the hardware realization.

f [kHz] EHCS VS

SNR [dB] 10 47,53 dB 46,22 dB
100 47,14 dB 46,25 dB

THD [dBc] 10 -42.31 -44.15
100 -35.17 -35.74