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Design of Low Leakage Current Average Power CMOS Current Comparator Using SVL Technique With Pseudo NMOS and Transmission Gate Logics


Cite

T.R. Dinesh Kumar
Faculty of Electronics and Communication Engineering,Vel TechChennai, India
K. Mohana Sundaram
Faculty of Electronics and Communication Engineering,Vel TechChennai, India
Faculty of Electrical and Electronics Engineering,Vel Tech Multitech Dr. Rangarajan Dr. Sakunthala Engineering CollegeChennai, India
M. Anto Bennet
Faculty of Electronics and Communication Engineering,Vel TechChennai, India
M. Pooja
UG Student of Electronics and Communication Engineering,Vel TechChennai, India
A.P. Kokila
UG Student of Electronics and Communication Engineering,Vel TechChennai, India
K. Anusuya
UG Student of Electronics and Communication Engineering,Vel TechChennai, India
eISSN:
1178-5608
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Temas de la revista:
Engineering, Introductions and Overviews, other