Radix-8 Design Alternatives of Fast Two Operands Interleaved Multiplication with Enhanced Architecture
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08. Okt. 2019
Über diesen Artikel
Online veröffentlicht: 08. Okt. 2019
Seitenbereich: 15 - 27
DOI: https://doi.org/10.21307/ijanmc-2019-043
Schlüsselwörter
© 2019 Mohammad M. Asad et al., published by Sciendo
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
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COMPARISON BETWEEN DESIGN II & DESIGN III_
| Design Solutions # | Delay (gate delay) | % Optimization | Area (# of gates) | % Optimization |
|---|---|---|---|---|
| Solution I: using KSA Adder. | 23 | +15% | 6130 | |
| Solution II: using Comparator unit. | 27 | 3712 | +50% |
RADIX-8 BOOTH ENCODING_
| Inputs (bits of M-bit multiplier) | Partial Product | |||
|---|---|---|---|---|
|
|
|
|
|
|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | A |
| 0 | 0 | 1 | 0 | A |
| 0 | 0 | 1 | 1 | 2A |
| 0 | 1 | 0 | 0 | 2A |
| 0 | 1 | 0 | 1 | 3A |
| 0 | 1 | 1 | 0 | 3A |
| 0 | 1 | 1 | 1 | 4A |
| 1 | 0 | 0 | 0 | -4A |
| 1 | 0 | 0 | 1 | -3A |
| 1 | 0 | 1 | 0 | -3A |
| 1 | 0 | 1 | 1 | -2A |
| 1 | 1 | 0 | 0 | -2A |
| 1 | 1 | 0 | 1 | -A |
| 1 | 1 | 1 | 0 | -A |
| 1 | 1 | 1 | 1 | 0 |