<abstract xmlns="http://www.w3.org/1999/xhtml"><p>In this paper a new structure of digital clock recovery — DCR circuit is presented. The main features of this DCR are: low complexity design, low power consumption and a single system clock operation. Thus, multiple instantiation of this type of DCR on a single chip is not complex. Due to this, such DCR can target application in energy-efficient cognitive radio systems with carrier aggregation. For performance evaluation, we have derived Markov chain based mathematical model for peak-to-peak and root mean square jitter performance analysis. The stability problem of this model, rising from the fact that some phase error states have several orders of magnitude lower probabilities than the others, is solved using mathematical apparatus for symbolic analysis. The mathematical model validity is examined by laboratorial measurements of proposed DCR for 4-PAM signal. The measurement methodology and results are described in details.</p></abstract>

In this paper a new structure of digital clock recovery — DCR circuit is presented. The main features of this DCR are: low complexity design, low power consumption and a single system clock operation. Thus, multiple instantiation of this type of DCR on a single chip is not complex. Due to this, such DCR can target application in energy-efficient cognitive radio systems with carrier aggregation. For performance evaluation, we have derived Markov chain based mathematical model for peak-to-peak and root mean square jitter performance analysis. The stability problem of this model, rising from the fact that some phase error states have several orders of magnitude lower probabilities than the others, is solved using mathematical apparatus for symbolic analysis. The mathematical model validity is examined by laboratorial measurements of proposed DCR for 4-PAM signal. The measurement methodology and results are described in details.

Low Power Consumption Digital Clock Recovery Circuit Based on Threshold Crossing

Vlatacom Institute of High Technologies, Blvd. M. Milankovića 5, 11070 Belgrade,

Journal of Electrical Engineering

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

{"article-title":"Low Power Consumption Digital Clock Recovery Circuit Based on Threshold Crossing"}

In this paper a new structure of digital clock recovery — DCR circuit is presented. The main features of this DCR are: low complexity design, low power...

Low Power Consumption Digital Clock Recovery Circuit Based on Threshold Crossing

Online veröffentlicht: 30. Dez. 2016

Seitenbereich: 433 - 438

Eingereicht: 27. Juni 2016

DOI: https://doi.org/10.1515/jee-2016-0063

Schlüsselwörter
synchronization, low power, jitter, Markov process

© 2016 Faculty of Electrical Engineering and Information Technology, Slovak University of Technology

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Low Power Consumption Digital Clock Recovery Circuit Based on Threshold Crossing

Online veröffentlicht: 30. Dez. 2016

Seitenbereich: 433 - 438

Eingereicht: 27. Juni 2016

DOI: https://doi.org/10.1515/jee-2016-0063

Schlüsselwörtersynchronization, low power, jitter, Markov process

© 2016 Faculty of Electrical Engineering and Information Technology, Slovak University of Technology

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Schlüsselwörter
synchronization, low power, jitter, Markov process