Digital Signal Processing Algorithm for Measurement of Settling Time of High-Resolution High-Speed DACs

The paper presents the developed complex Digital Signal Processing algorithm for the reduction of white and 1/f noise and processing of the measurement signals of the Settling Time Measurement of the Digital-to-Analog Converters. The results show that the proposed DSP algorithm ensures 100-fold suppression of the white noise and 1/f noise. It was shown that it is possible to measure settling times of highspeed DACs (up to 16-17 Bits) with readout levels of ± 0.5 LSB while measurement errors do no exceed ± 1.4 ns.

Language:: English

Publication timeframe:: 6 times per year
Journal Subjects:: Engineering, Electrical Engineering, Control Engineering, Metrology and Testing

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Digital Signal Processing Algorithm for Measurement of Settling Time of High-Resolution High-Speed DACs

Rokas Kvedaras

Vygaudas Kvedaras

Tomas Ustinavičius

Ričardas Masiulionis

Published Online: Jun 26, 2019

Page range: 86 - 92

Received: Jan 23, 2019

Accepted: May 30, 2019

DOI: https://doi.org/10.2478/msr-2019-0014

KeywordsDigital filters, active noise reduction, Discrete Fourier transforms, sampling method, time measurement, computerized instrumentation

© 2019 Rokas Kvedaras et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Keywords
Digital filters, active noise reduction, Discrete Fourier transforms, sampling method, time measurement, computerized instrumentation