Towards a design space exploration methodology for system-on-chip

1. Bakhouya, M. A Bio-Inspired Architecture for Autonomic Network-on-Chip. Autonomic Networkmg-on-Chip: Bio-Inspired Specification, Development, and Verification. - In: Embedded Multi-Core Systems (EMS) Book Series. Phan Cong-Vinh, Ed. Taylor and Francis/CRC. 2012, 1-20.10.1201/b11421-2Search in Google Scholar

2. Benini, L., G. D. Michel i. Networks on Chips: A New Socparadigm. - IEEE Computer, Vol. 35, 2002, No 1, 70-78.10.1109/2.976921Search in Google Scholar

3. Coppola, M., R. Locatelli, G. Maruccia, L. Pieralisi, A. Scandurra. Spidergon: A Novel On-Chip Communication Network. - In: Proc. of Inter. Symposium on System-on- Chip, 2004, 250-256.Search in Google Scholar

4. Guerrier, P., A. Greine r. A Generic Architecture for On-Chip Packet-Switched Interconnections. - DATE Proc., 2000, 250-256.10.1145/343647.343776Search in Google Scholar

5. Pande, P. P., C. Grec u, M. Jone s, A. Ivanov, R. Sale h. Performance Evaluation and Design Tradeoffs for Network-on-Chip Interconnect Architectures. - IEEE Trans. on Computer, Vol. 54, 2005, No 8, 1025-1040.10.1109/TC.2005.134Search in Google Scholar

6. Chariete, A., M. Bakhouya, J. Gabe r, M. Wack. An Approach for Customizing On- Chip Interconnect Architectures in So C Design. - HPCS’12, Madrid, Spain, 2012, 288-294.10.1109/HPCSim.2012.6266926Search in Google Scholar

7. Chariete, A., M. Bakhouya, J. Gabe r, M. Wack. Frac No C: A Fractal On-Chip Interconnect Architecture for System-on-Chip. - HPCS’13, Finland, 2013.10.1109/HPCSim.2013.6641416Search in Google Scholar

8. Chariete, A., M. Bakhouya, J. Gabe r, M. Wack, E. Coatanea, S. Niar. A Methodology for Customizing On-Chip Interconnect Architectures. Accepted with Revision in Concurrency and Computation - Practice & Experience Journal, 2013.10.1109/HPCSim.2012.6266926Search in Google Scholar

9. Bakhouya, M., A. Chariete, J. Gabe r, M. Wack. A Buffer-Space Allocation Approach for Application-Specific Network-on-Chip. - In: AICCSA’11, Egypte, 2011, 263-267.10.1109/AICCSA.2011.6126621Search in Google Scholar

10. Bakhouya, M., A. Chariete, J. Gabe r, M. Wack, S. Niar, E. Coatanea. Performance Evaluation ofa Flow Control Algorithm for Network-on-Chip. - In: HPCS’12, Spain, 2012, 281-287.10.1109/HPCSim.2012.6266925Search in Google Scholar

11. Bakhouya, M., S. Suboh, J. Gaber, T. El-Ghazawi, S. Niar. Performance Evaluation and Design Tradeoffs of On-Chip Interconnect Architectures. - SIMPAT Journal, Vol. 19, June 2011, Issue 6, 1496-1505.10.1016/j.simpat.2010.10.008Search in Google Scholar

12. Lavina, J. A Simulator for No C Interconnect Routing and Application Modeling, 2007. http://nirgam.ecs.soton.ac.uk/Search in Google Scholar

13. Suboh, S., M. Bakhouya, J. Gabe r, T. El-Ghazaw i. An Interconnection Architecture for Network-on-Chip Systems. - Telecom Systems, Vol. 37, 2008, No 1-3, 137-144.10.1007/s11235-008-9077-1Search in Google Scholar

14. Guffens, V., G. Bastin, H. Mounie r. Fluid Flow Network Modeling for Hop-By-Hop Feedback Control Design and Analysis. - In: Proceedings Internet-Working, 2003.Search in Google Scholar

15. Suboh, S., V. Narayana, M. Bakhouya, J. Gabe r, T. El-Ghazaw i. Methodology for Adapting On-Chip Interconnect Architectures. - IET Computers & Digital Techniques, 2003, 1-9. doi: 10.1049/iet-cdt.2013.0021.10.1049/iet-cdt.2013.0021Search in Google Scholar

16. De Florio, V., M. Bakhouya, A. Coronato, G. Di Marz o. Models and Concepts for Socio-Technical Complex Systems: Towards Fractal Social Organizations, Systems Research and Behavioral Science. - Syst. Res. Behav. Sci., 2013, 00:1-24.10.1002/sres.2242Search in Google Scholar

17. Chariete, A., M. Bakhouya, J. Gabe r, M. Wack. Towardsa Design Space Exploration Methodology for Application-Specific No C. - In: International Conference on High Performance Computing and Simulation (HPCS 2013), 224-228.Search in Google Scholar

18. Bakhouya, M., S. Subo h, J. Gabe r, T. El-Ghazaw i. Analytical Modeling and Evaluation of On-Chip Interconnects Using Network Calculus. - In: 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS’09), 74-79. Search in Google Scholar