<abstract xmlns="http://www.w3.org/1999/xhtml"><p> This paper provides an overview of a design space exploration methodology for customizing or tuning a candidate OCI architecture, given a resources budget and independent of a particular application traffic pattern. Three main approaches are introduced. The first approach allows customizing the On- Chip Interconnect by adding strategic long-rang links, while the second consists in customizing the buffer sizes at each switch according to the traffic. The third approach uses a feedback control-based mechanism for dynamic congestion avoidance. Some results are presented to shed more light on the usefulness of these approaches for System-on-Chip design.</p></abstract>

This paper provides an overview of a design space exploration methodology for customizing or tuning a candidate OCI architecture, given a resources budget and independent of a particular application traffic pattern. Three main approaches are introduced. The first approach allows customizing the On- Chip Interconnect by adding strategic long-rang links, while the second consists in customizing the buffer sizes at each switch according to the traffic. The third approach uses a feedback control-based mechanism for dynamic congestion avoidance. Some results are presented to shed more light on the usefulness of these approaches for System-on-Chip design.

Towards a design space exploration methodology for system-on-chip

Universite de Technologie de Belfort Montbéliard Rue Thierry Mieg, 90010 Belfort Cedex France

International University of Rabat ParcTechnopolis, 11 100 Sala el Jadida, Morocco

Cybernetics and Information Technologies

This article is distributed under the terms of the Creative Commons Attribution Non-Commercial License, which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

{"article-title":"Towards a design space exploration methodology for system-on-chip"}

This paper provides an overview of a design space exploration methodology for customizing or tuning a candidate OCI architecture, given a resources budget and...

Towards a design space exploration methodology for system-on-chip

Published Online: Apr 09, 2014

Page range: 101 - 111

DOI: https://doi.org/10.2478/cait-2014-0008

Keywords
System-on-Chip, On-chip interconnect, simulation, performance evaluation, design-space exploration

© by A. Chariete

This article is distributed under the terms of the Creative Commons Attribution Non-Commercial License, which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

Towards a design space exploration methodology for system-on-chip

Published Online: Apr 09, 2014

Page range: 101 - 111

DOI: https://doi.org/10.2478/cait-2014-0008

KeywordsSystem-on-Chip, On-chip interconnect, simulation, performance evaluation, design-space exploration

© by A. Chariete

This article is distributed under the terms of the Creative Commons Attribution Non-Commercial License, which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

Keywords
System-on-Chip, On-chip interconnect, simulation, performance evaluation, design-space exploration