Reducing the Phase-Noise In ΔΣ Fractional-N Synthezis – A Simulink Model

The resolution in fractional-N synthesis results as a fractional part of the reference frequency. This category of synthesizers permits a greater f_ref and a smaller N, a larger loop bandwidth, faster lock times and reduced output phase-noise. In ΔΣ fractional-N PLL’s the main problem is the specific quantization noise. To reduce them many techniques are used. The paper presents a Simulink model of the influence of the requantisation in the phase-noise cancellation process.