<abstract xml:lang="en" xmlns="http://www.w3.org/1999/xhtml"><p>We continue to formalize the concept of the Generalized Full Addition and Subtraction circuits (GFAs), define the structures of calculation units for the Redundant Signed Digit (RSD) operations, then prove its stability of the calculations. Generally, one-bit binary full adder assumes positive weights to all of its three binary inputs and two outputs. We define the circuit structure of two-types <italic>n</italic>-bit GFAs using the recursive construction to use the RSD arithmetic logical units that we generalize full adder to have both positive and negative weights to inputs and outputs. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.</p><p>MML identifier: GFACIRC2, version: 7.8.09 4.97.1001</p></abstract>

We continue to formalize the concept of the Generalized Full Addition and Subtraction circuits (GFAs), define the structures of calculation units for the Redundant Signed Digit (RSD) operations, then prove its stability of the calculations. Generally, one-bit binary full adder assumes positive weights to all of its three binary inputs and two outputs. We define the circuit structure of two-types n-bit GFAs using the recursive construction to use the RSD arithmetic logical units that we generalize full adder to have both positive and negative weights to inputs and outputs. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.MML identifier: GFACIRC2, version: 7.8.09 4.97.1001

Stability of <italic>n</italic>-Bit Generalized Full Adder Circuits (GFAs). Part II

Formalized Mathematics

Stability of -Bit Generalized Full Adder Circuits (GFAs). Part II

We continue to formalize the concept of the Generalized Full Addition and Subtraction circuits (GFAs), define the structures of calculation units for the...

Stability of n-Bit Generalized Full Adder Circuits (GFAs). Part II

Pubblicato online: 20 mar 2009

Pagine: 73 - 80

DOI: https://doi.org/10.2478/v10037-008-0011-5

This content is open access.