<abstract xml:lang="en" xmlns="http://www.w3.org/1999/xhtml"><p>This paper presents research on FPGA based acceleration of HPC applications. The most important goal is to extract a code that can be sped up. A major drawback is the lack of a tool which could do it. HPC applications usually consist of a huge amount of a complex source code. This is one of the reasons why the process of acceleration should be as automated as possible. Another reason is to make use of HLLs (High Level Languages) such as Mitrion-C (Mohl, 2006). HLLs were invented to make the development of HPRC applications faster. Loop profiling is one of the steps to check if the insertion of an HLL to an existing HPC source code is possible to gain acceleration of these applications. Hence the most important step to achieve acceleration is to extract the most time consuming code and data dependency, which makes the code easier to be pipelined and parallelized. Data dependency also gives information on how to implement algorithms in an FPGA circuit with minimal initialization of it during the execution of algorithms.</p></abstract>

This paper presents research on FPGA based acceleration of HPC applications. The most important goal is to extract a code that can be sped up. A major drawback is the lack of a tool which could do it. HPC applications usually consist of a huge amount of a complex source code. This is one of the reasons why the process of acceleration should be as automated as possible. Another reason is to make use of HLLs (High Level Languages) such as Mitrion-C (Mohl, 2006). HLLs were invented to make the development of HPRC applications faster. Loop profiling is one of the steps to check if the insertion of an HLL to an existing HPC source code is possible to gain acceleration of these applications. Hence the most important step to achieve acceleration is to extract the most time consuming code and data dependency, which makes the code easier to be pipelined and parallelized. Data dependency also gives information on how to implement algorithms in an FPGA circuit with minimal initialization of it during the execution of algorithms.

Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration

Department of Electrical Engineering and Computer Science, AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Cracow, Poland

Academic Computer Centre Cyfronet AGH, ul. Nawojki 11, 30-590 Cracow, Poland

International Journal of Applied Mathematics and Computer Science

This paper presents research on FPGA based acceleration of HPC applications. The most important goal is to extract a code that can be sped up. A major drawback...

Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration

Pubblicato online: 27 set 2010

Pagine: 581 - 589

DOI: https://doi.org/10.2478/v10006-010-0043-1

Parole chiave
HPC, HPRC (High Performance Reconfigurable Computing), loop profiling, Mitrion-C, DFG (Data Flow Graph)

This content is open access.

Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration

Pubblicato online: 27 set 2010

Pagine: 581 - 589

DOI: https://doi.org/10.2478/v10006-010-0043-1

Parole chiaveHPC, HPRC (High Performance Reconfigurable Computing), loop profiling, Mitrion-C, DFG (Data Flow Graph)

This content is open access.

Parole chiave
HPC, HPRC (High Performance Reconfigurable Computing), loop profiling, Mitrion-C, DFG (Data Flow Graph)