<abstract xmlns="http://www.w3.org/1999/xhtml"><p>The predictable CPU architectures that run hard real-time tasks must be executed with isolation in order to provide a timing-analyzable execution for real-time systems. The major problems for real-time operating systems are determined by an excessive jitter, introduced mainly through task switching. This can alter deadline requirements, and, consequently, the predictability of hard real-time tasks. New requirements also arise for a real-time operating system used in mixed-criticality systems, when the executions of hard real-time applications require timing predictability. The present article discusses several solutions to improve the performance of CPU architectures and eventually overcome the Operating Systems overhead inconveniences. This paper focuses on the innovative CPU implementation named nMPRA-MT, designed for small real-time applications. This implementation uses the replication and remapping techniques for the program counter, general purpose registers and pipeline registers, enabling multiple threads to share a single pipeline assembly line. In order to increase predictability, the proposed architecture partially removes the hazard situation at the expense of larger execution latency per one instruction.</p></abstract>

The predictable CPU architectures that run hard real-time tasks must be executed with isolation in order to provide a timing-analyzable execution for real-time systems. The major problems for real-time operating systems are determined by an excessive jitter, introduced mainly through task switching. This can alter deadline requirements, and, consequently, the predictability of hard real-time tasks. New requirements also arise for a real-time operating system used in mixed-criticality systems, when the executions of hard real-time applications require timing predictability. The present article discusses several solutions to improve the performance of CPU architectures and eventually overcome the Operating Systems overhead inconveniences. This paper focuses on the innovative CPU implementation named nMPRA-MT, designed for small real-time applications. This implementation uses the replication and remapping techniques for the program counter, general purpose registers and pipeline registers, enabling multiple threads to share a single pipeline assembly line. In order to increase predictability, the proposed architecture partially removes the hazard situation at the expense of larger execution latency per one instruction.

Improving the Performance of CPU Architectures by Reducing the Operating System Overhead (Extended Version)

Doctoral student, Stefan Cel Mare University of Suceava, Integrated Center for Research, Development and Innovation in Advanced Materials, Nanotechnologies, and Distributed Systems for Fabrication and Control (MANSiD)

Professor, Stefan Cel Mare University of Suceava, Integrated Center for Research, Development and Innovation in Advanced Materials, Nanotechnologies, and Distributed Systems for Fabrication and Control (MANSiD)

Electrical, Control and Communication Engineering

This work is licensed under the Creative Commons Attribution 4.0 Public License.

The predictable CPU architectures that run hard real-time tasks must be executed with isolation in order to provide a timing-analyzable execution for real-time...

Improving the Performance of CPU Architectures by Reducing the Operating System Overhead (Extended Version)

Pubblicato online: 18 gen 2017

Pagine: 13 - 22

DOI: https://doi.org/10.1515/ecce-2016-0002

Parole chiave
Jitter, Multithreading, Pipeline processing, Real-time systems, Scheduling

© 2016 Riga Technical University

This work is licensed under the Creative Commons Attribution 4.0 Public License.

Improving the Performance of CPU Architectures by Reducing the Operating System Overhead (Extended Version)

Pubblicato online: 18 gen 2017

Pagine: 13 - 22

DOI: https://doi.org/10.1515/ecce-2016-0002

Parole chiaveJitter, Multithreading, Pipeline processing, Real-time systems, Scheduling

© 2016 Riga Technical University

This work is licensed under the Creative Commons Attribution 4.0 Public License.

Parole chiave
Jitter, Multithreading, Pipeline processing, Real-time systems, Scheduling