<abstract xmlns="http://www.w3.org/1999/xhtml">

<p>Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of standard systems are reaching the limits of physics known to humankind. Fast, programmable systems with relatively low power consumption are a different concept for performing complex calculations. Highly parallel processing opens up a number of possibilities in the context of accelerating calculations. Application of SoC (System On Chip) with FPGA (Field-Programmable Gate Array) enables the delegating of a part of computations to the gates matrix, thereby expediting processing by using parallelization of hardware operations. This paper presents the general concept of using SoC FPGA systems to support the CPU (Central Processing Unit) in many modern tasks. While some tasks might be really hard to implement on an FPGA in a reasonable time, the SoC FPGA platform allows for easy low-level interconnections, and with such virtualized access to the hardware computing resources, it is seen as making FPGAs, or hardware in general, more accessible to engineers accustomed to high-level solutions. The concept presented in the article takes into account the limited resources of cheaper educational platforms, which, however, still provide an interesting and alternative hybrid solution to the problem of parallelization and acceleration of data processing. This allows encountered limitations to be overcome and the flexibility known from high-level solutions and high performance achieved with low-level programming to be maintained without the need for a high financial background.</p>
</abstract>

Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of standard systems are reaching the limits of physics known to humankind. Fast, programmable systems with relatively low power consumption are a different concept for performing complex calculations. Highly parallel processing opens up a number of possibilities in the context of accelerating calculations. Application of SoC (System On Chip) with FPGA (Field-Programmable Gate Array) enables the delegating of a part of computations to the gates matrix, thereby expediting processing by using parallelization of hardware operations. This paper presents the general concept of using SoC FPGA systems to support the CPU (Central Processing Unit) in many modern tasks. While some tasks might be really hard to implement on an FPGA in a reasonable time, the SoC FPGA platform allows for easy low-level interconnections, and with such virtualized access to the hardware computing resources, it is seen as making FPGAs, or hardware in general, more accessible to engineers accustomed to high-level solutions. The concept presented in the article takes into account the limited resources of cheaper educational platforms, which, however, still provide an interesting and alternative hybrid solution to the problem of parallelization and acceleration of data processing. This allows encountered limitations to be overcome and the flexibility known from high-level solutions and high performance achieved with low-level programming to be maintained without the need for a high financial background.

SOC-FPGA Based Concept of Hardware Aided Quantum Simulation

European Organization for Nuclear Research CERN

Journal of Automation, Mobile Robotics and Intelligent Systems

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

{"article-title":"SOC-FPGA Based Concept of Hardware Aided Quantum Simulation"}

Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of...

SOC-FPGA Based Concept of Hardware Aided Quantum Simulation

Pubblicato online: 23 giu 2024

Pagine: 17 - 23

Ricevuto: 24 feb 2023

Accettato: 13 lug 2023

DOI: https://doi.org/10.14313/jamris/2-2024/9

Parole chiave
FPGA, SoC, quantum circuit, parallel computing, web service, accelerating calculations

© 2024 Jacek Długopolski et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

SOC-FPGA Based Concept of Hardware Aided Quantum Simulation

Pubblicato online: 23 giu 2024

Pagine: 17 - 23

Ricevuto: 24 feb 2023

Accettato: 13 lug 2023

DOI: https://doi.org/10.14313/jamris/2-2024/9

Parole chiaveFPGA, SoC, quantum circuit, parallel computing, web service, accelerating calculations

© 2024 Jacek Długopolski et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Parole chiave
FPGA, SoC, quantum circuit, parallel computing, web service, accelerating calculations