<abstract xmlns="http://www.w3.org/1999/xhtml">

<p>A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes. The reduction is achieved due to the use of two-component state codes. Such an approach allows reducing the number of state variables compared with FSMs based on extended codes. There are exactly three levels of LUTs in the resulting FSM circuit. Each partial function is represented by a single-LUT circuit. The proposed method is illustrated with an example of synthesis. The experiments were conducted using standard benchmarks. They show that the proposed method produces FSM circuits with significantly smaller LUT counts compared with those produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of output collection codes into extended state codes). The LUT count is decreased by, on average, from 9.86% to 59.64%. The improvement of the LUT count is accompanied by a slightly improved performance. The maximum operating frequency is increased, on average, from 2.74% to 12.93%. The advantages of the proposed method become more pronounced with increasing values of FSM inputs and state variables.</p>
</abstract>

A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes. The reduction is achieved due to the use of two-component state codes. Such an approach allows reducing the number of state variables compared with FSMs based on extended codes. There are exactly three levels of LUTs in the resulting FSM circuit. Each partial function is represented by a single-LUT circuit. The proposed method is illustrated with an example of synthesis. The experiments were conducted using standard benchmarks. They show that the proposed method produces FSM circuits with significantly smaller LUT counts compared with those produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of output collection codes into extended state codes). The LUT count is decreased by, on average, from 9.86% to 59.64%. The improvement of the LUT count is accompanied by a slightly improved performance. The maximum operating frequency is increased, on average, from 2.74% to 12.93%. The advantages of the proposed method become more pronounced with increasing values of FSM inputs and state variables.

Improving the LUT Count for Mealy FSMS with Transformation of Output Collections

International Journal of Applied Mathematics and Computer Science

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

{"article-title":"Improving the LUT Count for Mealy FSMS with Transformation of Output Collections"}

A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of...

Improving the LUT Count for Mealy FSMS with Transformation of Output Collections

Publié en ligne: 08 oct. 2022

Pages: 479 - 494

Reçu: 09 déc. 2021

Accepté: 23 mars 2022

DOI: https://doi.org/10.34768/amcs-2022-0035

Mots clés
Mealy FSM, FPGA, LUT, synthesis, state codes

© 2022 Alexander Barkalov et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Improving the LUT Count for Mealy FSMS with Transformation of Output Collections

Publié en ligne: 08 oct. 2022

Pages: 479 - 494

Reçu: 09 déc. 2021

Accepté: 23 mars 2022

DOI: https://doi.org/10.34768/amcs-2022-0035

Mots clésMealy FSM, FPGA, LUT, synthesis, state codes

© 2022 Alexander Barkalov et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Mots clés
Mealy FSM, FPGA, LUT, synthesis, state codes