<abstract xml:lang="en" xmlns="http://www.w3.org/1999/xhtml"><p>The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.</p></abstract>

The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.

Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction

School of Electrical and Electronic Engineering, The University of Adelaide, South Australia 5005, Australia

Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600, Bangi, Selangor, Malaysia

Measurement Science Review

{"article-title":"Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction"}

The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated...

Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction

Publié en ligne: 19 avr. 2012

Pages: 52 - 55

DOI: https://doi.org/10.2478/v10048-012-0007-8

Mots clés
Fetal electrocardiogram, neural network, FPGA, VHDL

This content is open access.

Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction

Publié en ligne: 19 avr. 2012

Pages: 52 - 55

DOI: https://doi.org/10.2478/v10048-012-0007-8

Mots clésFetal electrocardiogram, neural network, FPGA, VHDL

This content is open access.

Mots clés
Fetal electrocardiogram, neural network, FPGA, VHDL