<abstract xml:lang="en" xmlns="http://www.w3.org/1999/xhtml"><p>The paper presents a new two-step approach to FSM synthesis for PAL-based CPLDs that strives to find an optimum fit of an FSM to the structure of the CPLD. The first step, the original state assignment method, includes techniques of two-level minimization and aims at area minimization. The second step, PAL-oriented multi-level optimization, is a search for implicants that can be shared by several functions. It is based on the graph of outputs. Results of experiments prove that the presented approach is especially effective for PAL-based CPLD structures containing a low number of product terms.</p></abstract>

The paper presents a new two-step approach to FSM synthesis for PAL-based CPLDs that strives to find an optimum fit of an FSM to the structure of the CPLD. The first step, the original state assignment method, includes techniques of two-level minimization and aims at area minimization. The second step, PAL-oriented multi-level optimization, is a search for implicants that can be shared by several functions. It is based on the graph of outputs. Results of experiments prove that the presented approach is especially effective for PAL-based CPLD structures containing a low number of product terms.

Synthesis of finite state machines for CPLDs

Institute of Electronics, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland

International Journal of Applied Mathematics and Computer Science

{"article-title":"Synthesis of finite state machines for CPLDs"}

The paper presents a new two-step approach to FSM synthesis for PAL-based CPLDs that strives to find an optimum fit of an FSM to the structure of the CPLD. The...

Synthesis of finite state machines for CPLDs

Publié en ligne: 31 déc. 2009

Pages: 647 - 659

DOI: https://doi.org/10.2478/v10006-009-0052-0

Mots clés
logic synthesis, FSM, state assignment, logic optimization, CPLD

This content is open access.

Synthesis of finite state machines for CPLDs

Publié en ligne: 31 déc. 2009

Pages: 647 - 659

DOI: https://doi.org/10.2478/v10006-009-0052-0

Mots cléslogic synthesis, FSM, state assignment, logic optimization, CPLD

This content is open access.

Mots clés
logic synthesis, FSM, state assignment, logic optimization, CPLD