<abstract xml:lang="en" xmlns="http://www.w3.org/1999/xhtml"><p>We address the problem of encoding the state variables of a finite state machine such that the BDD representing the next state function and the output function has the minimum number of nodes. We present an exact algorithm to solve this problem when only the present state variables are encoded. We provide results on MCNC benchmark circuits.</p></abstract>

We address the problem of encoding the state variables of a finite state machine such that the BDD representing the next state function and the output function has the minimum number of nodes. We present an exact algorithm to solve this problem when only the present state variables are encoded. We provide results on MCNC benchmark circuits.

FSM Encoding for BDD Representations

Cadence Design Systems, 2655 Seely Avenue, San Jose, CA 95134

Universita' di Verona, Ca' Vignal 2, Strada Le Grazie 15, 37134 Verona, Italy, tiziano.villa@univr.it

Exponential Interactive, Inc., Emeryville, CA 94608, USA

Department of Electrical Engineering and Computer Sience, University of California, Berkeley, CA 94720, USA

International Journal of Applied Mathematics and Computer Science

{"article-title":"FSM Encoding for BDD Representations"}

We address the problem of encoding the state variables of a finite state machine such that the BDD representing the next state function and the output function...

FSM Encoding for BDD Representations

Publié en ligne: 05 avr. 2007

Pages: 113 - 124

DOI: https://doi.org/10.2478/v10006-007-0011-6

Mots clés
binary decision diagram, encoding, finite state machine, logic synthesis, formal verification, logic representation

This content is open access.

FSM Encoding for BDD Representations

Publié en ligne: 05 avr. 2007

Pages: 113 - 124

DOI: https://doi.org/10.2478/v10006-007-0011-6

Mots clésbinary decision diagram, encoding, finite state machine, logic synthesis, formal verification, logic representation

This content is open access.

Mots clés
binary decision diagram, encoding, finite state machine, logic synthesis, formal verification, logic representation