<abstract xmlns="http://www.w3.org/1999/xhtml">

<p>In this paper, a three-phase shunt active power filter (SAPF) controller with a fully digital implementation is presented. The main goal of this contribution is to implement a digital direct power control (DDPC) algorithm without phase-locked-loop (PLL) for SAPF. This algorithm is intended for power quality improvement and current harmonic elimination. The controller introduced in this paper is cost-effective, has a fast-dynamic response, and has a simple hardware implementation. In order to comply with the above specifications, a dedicated controller has been conceived and fully implemented within a field-programmable gate array (FPGA) device. This FPGA-based controller integrates the whole signal-processing functions needed to drive the SAPF, as well as an original method for sector identification. The intended controller provides the desired power references to select the optimal switching sequences. The switching orders follow the grid reference to drive the voltage source inverter (VSI), so the SAPF achieves good performances while ensuring balanced overall supply currents, unity power factor, and reduced harmonic load currents. The proposed digital implementation achieves a valuable compromise between fast dynamic response, minimum execution time, and reduced FPGA resources, through a simple hardware design implementation. The entire system is developed and simulated using VHDL and VHDL-AMS languages.</p>
</abstract>

In this paper, a three-phase shunt active power filter (SAPF) controller with a fully digital implementation is presented. The main goal of this contribution is to implement a digital direct power control (DDPC) algorithm without phase-locked-loop (PLL) for SAPF. This algorithm is intended for power quality improvement and current harmonic elimination. The controller introduced in this paper is cost-effective, has a fast-dynamic response, and has a simple hardware implementation. In order to comply with the above specifications, a dedicated controller has been conceived and fully implemented within a field-programmable gate array (FPGA) device. This FPGA-based controller integrates the whole signal-processing functions needed to drive the SAPF, as well as an original method for sector identification. The intended controller provides the desired power references to select the optimal switching sequences. The switching orders follow the grid reference to drive the voltage source inverter (VSI), so the SAPF achieves good performances while ensuring balanced overall supply currents, unity power factor, and reduced harmonic load currents. The proposed digital implementation achieves a valuable compromise between fast dynamic response, minimum execution time, and reduced FPGA resources, through a simple hardware design implementation. The entire system is developed and simulated using VHDL and VHDL-AMS languages.

Enhanced FPGA-Based Controller for Three Phase Shunt Active Power Filter

abdelouahabdjoubair.benhamadouche@univ-msila.dz

Power Electronics and Drives

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

{"article-title":"Enhanced FPGA-Based Controller for Three Phase Shunt Active Power Filter"}

In this paper, a three-phase shunt active power filter (SAPF) controller with a fully digital implementation is presented. The main goal of this contribution...

Enhanced FPGA-Based Controller for Three Phase Shunt Active Power Filter

Publié en ligne: 21 avr. 2023

Pages: 128 - 141

Reçu: 03 mars 2023

Accepté: 30 mars 2023

DOI: https://doi.org/10.2478/pead-2023-0010

Mots clés
Shunt active power filter, direct power control, harmonic elimination, reactive power compensation, field-programmable gate array

© 2023 Abdelouahab Djoubair Benhamadouche et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Enhanced FPGA-Based Controller for Three Phase Shunt Active Power Filter

Publié en ligne: 21 avr. 2023

Pages: 128 - 141

Reçu: 03 mars 2023

Accepté: 30 mars 2023

DOI: https://doi.org/10.2478/pead-2023-0010

Mots clésShunt active power filter, direct power control, harmonic elimination, reactive power compensation, field-programmable gate array

© 2023 Abdelouahab Djoubair Benhamadouche et al., published by Sciendo

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Mots clés
Shunt active power filter, direct power control, harmonic elimination, reactive power compensation, field-programmable gate array