Defect-minimized directly grown graphene-based solar cells

Graphene, as a new material, has received extensive attention from many different fields since its inception. Because of its adjustable work function [1, 2], extraordinary conductivity [3], high optical transparency, and high stability [4, 5], graphene has gained more attention in the field of photovoltaics [6, 7]. The power conversion efficiency (PCE) of crystalline silicon solar cells has reached >26% and occupied most of the market share [8], but high temperature and cost occur inevitably during the ion doping process [9]. The fabrication of solar cells with low consumption and cost is urgently needed in the industrialization of the world. Therefore, graphene-based solar cells have been developed rapidly.

The PCE of graphene-based solar cells obtained by the transfer method was rapidly improved from 1.5% in 2010 [10,11,12]. The efficiency of graphene/GaAs reached 18.5% as far back as 2015 [12]. However, the transfer method will lead to serious damage to graphene, such as contaminants, wrinkles, and tears [13, 14], which are bad for the cell performance and are not suitable for the current industrial development. In 2015, Liu et al. [15] first manufactured graphene nanowalls/Si (GNWs/Si) solar cells via direct growth of GNWs on the Si substrate by plasma-enhanced chemical vapor deposition (PECVD) and obtained a PCE of 3.5%. The PECVD direct growth method is compatible with the current industrialization and has excellent competitiveness. However, many defects exist in the GNWs with quite a lot of open edges, which will introduce a large number of recombination centers and damage the performance of solar cells [16]. The defects can be reduced by adjusting the growth conditions of graphene or introducing a passivation layer. Researchers were more interested in the latter, and the former seems to be neglected. Muhammad Fahad Bhopal et al. [17] and Malik Abdul Rehman et al. [18], respectively, demonstrated that the defects in graphene can be reduced by introducing HfO₂ and Al₂O₃ as an interfacial layer for the graphene/silicon (Gr/Si) solar cells, whereby PCEs reached up to 4.54% and 8.4%, respectively. In 2020, Malik Abdul Rehman et al. [19] reduced the graphene defects by co-doping with HNO₃ and poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) and achieved a PCE of 10.97%. In 2021, through an interfacial layer of NH₃-H₂O₂ co-passivated Al₂O₃, Kim et al. [20] exhibited a PCE of 9.49% for the direct growth graphene/Si solar cells. However, there is no research report on how to reduce defects in graphene by adjusting the growth conditions of graphene to improve the performance of Gr/Si solar cells. For graphene films rather than solar cell devices, the defects can be reduced in a straightforward way, such as by simply increasing the graphene growth time or temperature [15, 21]. However, increasing growth time or temperature will inevitably reduce the sheet resistance and transmittance. The balance relation between sheet resistivity and transmittance has been discussed in-depth for Gr/Si solar cells in previous reports [7, 15]. How to reduce the defects by improving the quality of graphene is not an easy problem under the condition of maintaining appropriate sheet resistance.

In this work, we minimized the defects in GNWs via two paths: improving the quality of GNWs itself and passivating to improve the efficiency of directly grown GNWs-based solar cells. To begin with, we demonstrated that the defects in GNWs can be reduced by simultaneously lowering the growth temperature and increasing the growth time under the premise of maintaining the appropriate sheet resistance of GNWs. Then, a PCE of 3.83% was achieved by minimizing the defects in GNWs for ensuring their adequate coverage on the bare planar silicon. Finally, the defects in the GNWs were further reduced by adding a poly(3,4-ethylenedioxythiophene) (PEDOT): Nafion passivation coating, and the PCE was significantly improved to 10.55%. This work demonstrates an innovative path and a simple approach to minimize the defects in graphene grown directly on silicon for high-efficiency solar cells.

By simultaneously changing the growth time and temperature, four GNW growth conditions with the appropriate sheet resistance (about 1.3 kΩ/sq) are obtained, which are 610°C – 70 min, 600°C – 80 min, 590°C – 100 min, and 580°C – 120 min, respectively. The specific sheet resistance after adjustment is shown in Figure 1A. For the sake of contrast, the optimized sheet resistance of graphene and the performance of the highest-efficiency cells in previous reports are summarized in Table 1. The sheet resistance of graphene of these highest efficiency cells is generally between 0.8 kΩ/sq and 1.6 kΩ/sq; the sheet resistance (about 1.3 kΩ/sq) of GNWs in the present work is also in this range.

Fig. 1

Raman spectrum is an essential tool for graphene research [16, 24, 25]. The Raman spectra of graphene grown directly on bare polished silicon at different growth temperatures are shown in Figure 1B. All samples have three Raman peaks: D peak 1,344 cm⁻¹, G peak 1,580 cm⁻¹, and 2D band around 2,687 cm⁻¹. In addition, the acromion (G′ peak 1,618 cm⁻¹) can also be seen. The G′ and D peaks indicate the structural disorder and defects in graphene. The ultimate nature of graphene can be confirmed by the 2D band and the G peak reveals the pairs of graphene [16, 26,27,28]. The I_D/I_G ratio is often used to evaluate the defect density in graphene. As shown in Figure 1C, with an increase in growth temperature and a reduction in growth time, the value of I_D/I_G increases, implying more defects and poorer quality of GNWs. The lowest value (1.02) of I_D/I_G indicates minimum defects at 580°C – 120 min. At 590°C – 100 min, 600°C – 80 min, and 610°C – 70 min, the values of I_D/I_G are 1.41, 1.43, and 1.72, respectively. The decreasing tendency of I_2D/I_G (from 0.51 to 0.41) with a decrease in growth time and increase in growth temperature implies a reduction in GNW thickness.

The surface morphology of the GNWs with the simultaneous variation of growth temperature and growth time is revealed by the test result of AFM in Figures 1D–1G. The thickness of GNWs is decreasing with a decrease in the growth time and increase in the growth temperature, which is in good agreement with the results of Raman spectrum. The thickness of the GNWs reaches >100 nm at 580°C – 120 min, while the coverage of the GNWs on the silicon surface is low. With an increase in the growth temperature and a decrease in the growth time, the coverage of GNWs increases. At 600°C – 80 min, GNWs has almost covered the whole surface of the silicon wafer. When the experimental condition is 610° C – 70 min, the GNWs cover the whole silicon surface and the thickness of GNWs is only >60 nm.

To ensure repeatability and reproducibility, multiple (not less than 8 in each group) solar cells were prepared and tested, and the results are shown in Figure 1H. With the increase in growth temperature and decrease in growth time, the efficiency increases first and then decreases. The defects in GNWs are least at 580°C – 120 min, but the PCE (2.26%) of the solar cell is the lowest. It is easy to infer that the lowest PCE is due to the low coverage of GNWs and discontinuous film. With the increase in growth time and reduction in growth temperature, although the defects increase, the efficiency is significantly improved because of the increase in the coverage of GNWs. The efficiency reaches up to 3.6% at 590°C – 100 min, and the highest efficiency of 3.83 is achieved at 600°C – 80 min. From 600°C – 80 min to 610°C – 70 min, the coverage no longer plays a major role in affecting the cell performance. Concurrently, the conclusion that defects in GNWs increase can be confirmed on the basis of the significant increase in the I_D/I_G ratio from 1.43 to 1.72 (Figure 1C), which leads to a noticeable decrease in PCE.

Devices with the highest efficiency in each experimental group were selected for further study. The I–V curve and the EQE are shown in Figures 2A and 2B; there is a good correspondence between the two groups of results. The performance parameters V_oc, J_sc, FF, and PCE are illustrated in Table 2.

Fig. 2

The quality of the diode can be evaluated by characterizing the dark J–V. The J–V relationship can be described as [29] (1) J=J0{exp[qAkT(V−JRS)]−1} + V−JRSRSH \matrix{{J = {J_0}\left\{ {\exp \left[ {{q \over {AkT}}\left( {V - J{R_S}} \right)} \right] - 1} \right\}} \hfill \cr {\;\;\; + {{V - J{R_S}} \over {{R_{SH}}}}} \hfill \cr } where J₀ is the reverse saturation current and n is the ideality factor of the device, q is the electric charge, T is the absolute temperature, and K is the Boltzmann constant. Eq. (1) is insoluble, but the device parameters can be approximately extracted by some algorithms [29]. Ignoring 1 in the parentheses and assuming R_SH is infinite, Eq. (1) can be simplified as [29] (2) dVdJ=RS+AkTqJ−1 {{dV} \over {dJ}} = {R_S} + {{AkT} \over q}{J^{ - 1}}

By plotting dV/dJ vs. J⁻¹ in the forward bias region, as shown in Figure 2C, R_S and n can be extracted. The R_S of the device at 580°C – 120 min is the highest, which could be due to the discontinuity of conductive channels due to the low coverage of GNWs. R_S decreases with an increase in growth temperature. When the growth temperature reaches 600°, R_S decreases to the lowest value at 3.41upΩ·cm² as the GNWs have almost covered the entire surface of the silicon wafer. Here, the n is ignored because of the assumptions of R_SH.

Arranging Eq. (1) again, we can get [29] (3) log(J−V−JRSRSH)=logJ0e + q(V−JRS)AkTloge \matrix{{\log \left( {J - {{V - J{R_S}} \over {{R_{SH}}}}} \right) = \log {{{J_0}} \over e}} \hfill \cr {\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\; + {{q\left( {V - J{R_S}} \right)} \over {AkT}}} \log e\hfill \cr }

R_SH may be obtained from the slope near 0V in the dark J–V curve. R_S has been extracted from the above results. By plotting log[J − (J −V R_S)/R_SH] vs. (V − JR_S) near the forward bias region, as shown in Figure 2D, J₀ and n can be extracted.

At 580°C–120 min, the defects in GNWs are the least; however, the highest n and higher J₀ are obtained due to the high R_S as the low coverage of GNWs. The high R_S not only directly results in the high n and low FF, but also leads to high J₀ and low V_oc as the high R_S enhances the recombination rate. Besides, the low light absorption of silicon due to thicker GNWs leads to a reduction in J_sc. Compared with 580°C – 120 min, the n and J₀ decrease and the FF and V_oc improve at 590°C – 100 min, which is due to the decrease in R_S with a significant increase in the coverage of GNWs. Meanwhile, the J_sc increases with decreasing thickness of GNWs. The PCE was improved to 3.6%, which is only a little lower than that of 600°C – 80 min. From 590°C – 100 min to 600°C – 80 min, the carrier recombination center increases with an increase in GNW defects, while the reduction of R_S indicates that carrier recombination will be inhibited, making n slightly lower and J₀ close. The thinner thickness of GNWs ensures the higher J_sc. Therefore, PCE at 600°C – 80 min is higher than that at 590°C – 100 min. When the experimental condition is 610°C – 70 min, according to the high I_D/I_G ratio and high J₀, we infer that an increase in GNW defects leads to a significant drop in V_oc, resulting in a reduction in PCE. In summary, under the condition of ensuring adequate coverage of GNWs on silicon and appropriate sheet resistance of GNWs, the PCE of GNW solar cells can be improved by concurrently reducing the growth temperature and increasing the growth time to minimize the defects in GNWs.

To reduce the defects in GNWs and further improve the performance of solar cells, the GNWs were modified by adding a PEDOT:Nafion coating with conductivity and passivation [22]. The SEM images shown in Figures 3A and 3B manifest that the thickness of PEDOT: Nafion coating and pristine GNWs are the same. The device structure diagram of the solar cell after adding PEDOT: Nafion coating is shown in Figure 3C.

Fig. 3

Figure 4A presents a comparison of the light J–V characteristics of solar cells with the PEDOT:Nafion coating and pristine GNWs. Meanwhile, the diode quality of the sample with PEDOT:Nafion coating on the pristine GNWs is evaluated according to the dark J–V characteristic (Figures 4C and 4D). Cell performance after adding the PEDOT:Nafion coatings was improved, as V_oc, J_sc, FF, and PCE were 0.557 V, 29.56 mA/cm², 64.09%, and 10.55%, respectively.

Fig. 4

From Figures 4C and 4D, we can see that the value of n decreases from 1.26 to 1.12 and the J₀ decreases nearly 65% (from 3.12 × 10⁻⁷ to 1.08 × 10⁻⁷A/cm²) after adding the PEDOT:Nafion coating. The decrease in J₀ indicates the reduction in GNW defects, which obviously benefited from the passivation of the PEDOT:Nafion coatings. One reason for the reduction in n is the passivation of PEDOT: Nafion coatings, another reason will be given in the following. The decrease of J₀ and n indicates that the V_oc and FF are improved. In addition to passivation, the PEDOT:Nafion coatings have many other functions in improving the cell performance. On one hand, the thin PEDOT: Nafion coating not only guarantees high transmittance (Figure 5A), but also greatly reduces the reflectivity (Figure 5B). The reflectivity of the sample with PEDOT:Nafion coating could be as low as ~17% in the range of 550–1000 nm. Clearly, the enhanced J_sc is mainly related to the increment of light absorption, because the PEDOT:Nafion coating reduces the reflectivity. On the other hand, the UPS test results in Figure 5C show that the work function of GNWs was increased from 4.37 eV to 4.9 eV after the addition of Nafion:PEDOT coatings, which indicates a p-doping by PEDOT: Nafion coatings. The increase in work function of GNWs would result in an increase in the built-in voltage of the GNWs/Si Schottky junction, which further increases the V_oc. Last but not least, as an important parameter, the sheet resistance is a great obstacle to improving the PCE of GNW solar cells. Due to the excellent conductivity of the PEDOT:Nafion coating, the sheet resistance is reduced from 1.3 kΩ/sq to 0.6 kΩ/sq. Reduced sheet resistance results in a decrease in R_S from 3.41 Ω·cm² to 0.76 Ω·cm², which further improves the n and FF on the basis of passivation.

Fig. 5

The defects in GNWs were minimized via two paths: improving the quality of GNWs itself and passivating to improve the efficiency of directly grown GNW-based solar cells. By simultaneously lowering the growth temperature and increasing the growth time, the defects in GNWs can be reduced under the premise of keeping the appropriate sheet resistance of GNWs. The PCE of 3.83% was achieved by minimizing the defects in GNWs under the condition of making sure of adequate coverage of GNWs on the bare planar silicon. The GNW defects were further reduced by adding a PEDOT:Nafion passivating coating, and the PCE was significantly improved to 10.55%. This work demonstrates an innovative path and a simple approach to minimize the defects in graphene grown directly on silicon for high-efficiency solar cells.